Professor Sri Parameswaran

Professor Sri Parameswaran

Adjunct Professor

PhD - The University of Queensland

B.Eng - Monash University

Engineering
Computer Science and Engineering

Sri Parameswaran is a Professor in the School of Computer Science and Engineering at the University of New South Wales. He was in the role of  Acting Head of School at the University of New South Wales from 2019 to 2020. He served as the Program Director for Computer Engineering.   His research interests are in System Level Synthesis, Low power systems, High Level Systems and Network on Chips. He also  served as the Editor in Chief of the IEEE Embedded Systems Letters from 2016 to 2019. He serves or has served on the editorial boards of  IEEE Transactions on Computer Aided Design, ACM Transactions on Embedded Computing Systems, the EURASIP Journal on Embedded Systems and the Design Automation of Embedded Systems. He has  served on the Program Committees of Design Automation Conference (DAC), Design and Test in Europe (DATE), the International Conference on Computer Aided Design (ICCAD), the International Conference on Hardware/Software Code-sign and System Synthesis (CODES-ISSS), and  the International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES). Sri Parameswaran received his B.Eng Degree from Monash University and his PhD from The University of Queensland.

    Phone
    +61 2 9385 7223
    Location
    Building K17 Kensington Campus
    • Books | 2024
      , 2024, Security, Privacy, and Applied Cryptography Engineering, Regazzoni F; Mazumdar B; Parameswaran S, (eds.), Springer Nature Switzerland, http://dx.doi.org/10.1007/978-3-031-51583-5
      Books | 2013
      Javaid H; Parameswaran S, 2013, Pipelined Multiprocessor System-on-Chip for Multimedia, Springer
      Books | 2010
      Ambrose JA; Ignjatovic A; Parameswaran S, 2010, Power Analysis Side Channel Attacks: The Processor Design-level Context, Original, VDM Verlag Dr. Müller, Germany, http://www.amazon.com/Power-Analysis-Side-Channel-Attacks/dp/3836485087
      Books | 2008
      Guo HA; Parameswaran S; Radhakrishnan S, 2008, Heterogeneous multi-pipeline ASIP, Original, VDM Verlag, Germany
      Books | 2007
      Henkel J; Parameswaran S, 2007, Designing embedded processors: A low power perspective, http://dx.doi.org/10.1007/978-1-4020-5869-1
    • Book Chapters | 2024
      Jayasinghe D; Parameswaran S, 2024, 'SRISC: Open Source Soft Processor Side Channel Analysis Attack Framework Using RISC-V', in , pp. 112 - 124, http://dx.doi.org/10.1007/978-3-031-51135-6_10
      Book Chapters | 2024
      Regazzoni F; Mazumdar B; Parameswaran S, 2024, 'Preface', in Security, Privacy, and Applied Cryptography Engineering
      Book Chapters | 2019
      Lehmann T; Aluthwala P; Parameswaran S, 2019, 'Digitally enhanced digital-to-analogue converters', in Digitally Enhanced Mixed Signal Systems, pp. 227 - 254
      Book Chapters | 2017
      Bokhari H; Parameswaran S, 2017, 'Network-on-chip design', in Handbook of Hardware Software Codesign, pp. 461 - 489, http://dx.doi.org/10.1007/978-94-017-7267-9_16
      Book Chapters | 2017
      Bokhari H; Shafique M; Henkel J; Parameswaran S, 2017, 'Adroit use of dark silicon for power, performance and reliability optimisation of NoCs', in Rahmani A; Liljeberg P; Hemani A; Jantsch A; Tenhunen H (ed.), The Dark Side of Silicon: Energy Efficient Computing in the Dark Silicon Era, Springer, pp. 291 - 325, http://dx.doi.org/10.1007/978-3-319-31596-6_11
      Book Chapters | 2016
      Bokhari H; Parameswaran S, 2016, 'Network-on-Chip Design', in Handbook of Hardware/Software Codesign, Springer Netherlands, pp. 1 - 29, http://dx.doi.org/10.1007/978-94-017-7358-4_16-1
      Book Chapters | 2016
      Cetin E; Diessel O; Li T; Ambrose J; Fisk T; Parameswaran S; Dempster A, 2016, 'Overview and Investigation of SEU Detection and Recovery Approaches for FPGA-Based Heterogeneous Systems', in FPGAs and Parallel Architectures for Aerospace Applications Soft Errors and Fault-Tolerant Design, Springer, pp. 33 - 46, http://dx.doi.org/10.1007/978-3-319-14352-1_3
      Book Chapters | 2007
      Henkel J; Parameswaran S; Cheung N, 2007, 'Application-specific embedded processors', in Designing Embedded Processors A Low Power Perspective, pp. 3 - 23, http://dx.doi.org/10.1007/978-1-4020-5869-1_1
      Book Chapters | 2007
      Henkel J; Parameswaran S, 2007, 'Foreword: Embedded processors -What is next?', in , pp. xv - xviii, http://dx.doi.org/10.1007/978-1-4020-5869-1
      Book Chapters | 2007
      Parameswaran S; Henkel J; Cheung N, 2007, 'Chapter 11 Instruction Matching and Modeling', in Customizable Embedded Processors, Elsevier, pp. 257 - 280, http://dx.doi.org/10.1016/b978-012369526-0/50012-7
      Book Chapters | 2003
      Cheung NL; Henkel J; Parameswaran S, 2003, 'Rapid Configuration & Instruction Selection for an ASIP:a Case Study', in Jerraya A; Yoo S; Verkest D; Wehn N (ed.), Embedded Software for, Kluwer Academic Publishers, Boston, USA, pp. 403 - 417
    • Edited Books | 2024
      Regazzoni F; Mazumdar B; Parameswaran S, (eds.), 2024, Security, Privacy, and Applied Cryptography Engineering, Springer Nature Switzerland, http://dx.doi.org/10.1007/978-3-031-51583-5
    • Journal articles | 2025
      Samarakoon H; Wan YK; Parameswaran S; Göke J; Gamaarachchi H; Deveson IW, 2025, 'Leveraging basecaller’s move table to generate a lightweight k-mer model for nanopore sequencing analysis', Bioinformatics, 41, http://dx.doi.org/10.1093/bioinformatics/btaf111
      Journal articles | 2024
      Gamaarachchi H; Ferguson JM; Samarakoon H; Liyanage K; Deveson IW, 2024, 'Simulation of nanopore sequencing signal data with tunable parameters', Genome Research, 34, pp. 778 - 783, http://dx.doi.org/10.1101/gr.278730.123
      Journal articles | 2024
      Hussain S; Guo H; Li T; Parameswaran S, 2024, 'MP-ORAM: A Novel ORAM Design for Multicore Processor Systems', IEEE Transactions on Dependable and Secure Computing, 21, pp. 3719 - 3733, http://dx.doi.org/10.1109/TDSC.2023.3337114
      Journal articles | 2024
      Samarakoon H; Liyanage K; Ferguson JM; Parameswaran S; Gamaarachchi H; Deveson IW, 2024, 'Interactive visualization of nanopore sequencing signal data with Squigualiser', Bioinformatics, 40, http://dx.doi.org/10.1093/bioinformatics/btae501
      Journal articles | 2023
      Bosio A; Dolecek L; Kourfali A; Parameswaran S; Savino A, 2023, 'Special Issue: "Approximation at the Edge"', ACM Transactions on Embedded Computing Systems, 22, http://dx.doi.org/10.1145/3605757
      Journal articles | 2023
      Gong J; Saadat H; Gamaarachchi H; Javaid H; Hu XS; Parameswaran S, 2023, 'ApproxTrain: Fast Simulation of Approximate Multipliers for DNN Training and Inference', IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 42, pp. 3505 - 3518, http://dx.doi.org/10.1109/TCAD.2023.3253045
      Journal articles | 2023
      Jayasinghe D; Udugama B; Parameswaran S, 2023, '1LUTSensor: Detecting FPGA Voltage Fluctuations using LookUp Tables', Iacr Transactions on Cryptographic Hardware and Embedded Systems, 2024, pp. 51 - 86, http://dx.doi.org/10.46586/tches.v2024.i1.51-86
      Journal articles | 2023
      Liyanage K; Gamaarachchi H; Ragel R; Parameswaran S, 2023, 'Cross Layer Design Using HW/SW Co-Design and HLS to Accelerate Chaining in Genomic Analysis', IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 42, pp. 2924 - 2937, http://dx.doi.org/10.1109/TCAD.2023.3236559
      Journal articles | 2023
      Liyanage K; Samarakoon H; Parameswaran S; Gamaarachchi H, 2023, 'Efficient end-to-end long-read sequence mapping using minimap2-fpga integrated with hardware accelerated chaining', Scientific Reports, 13, http://dx.doi.org/10.1038/s41598-023-47354-8
      Journal articles | 2023
      Samarakoon H; Ferguson JM; Jenner SP; Amos TG; Parameswaran S; Gamaarachchi H; Deveson IW, 2023, 'Flexible and efficient handling of nanopore sequencing signal data with slow5tools', Genome Biology, 24, http://dx.doi.org/10.1186/s13059-023-02910-3
      Journal articles | 2023
      Shih PJ; Saadat H; Parameswaran S; Gamaarachchi H, 2023, 'Efficient real-time selective genome sequencing on resource-constrained devices', Gigascience, 12, http://dx.doi.org/10.1093/gigascience/giad046
      Journal articles | 2022
      Gamaarachchi H; Samarakoon H; Jenner SP; Ferguson JM; Amos TG; Hammond JM; Saadat H; Smith MA; Parameswaran S; Deveson IW, 2022, 'Fast nanopore sequencing data analysis with SLOW5', Nature Biotechnology, 40, pp. 1026 - 1029, http://dx.doi.org/10.1038/s41587-021-01147-4
      Journal articles | 2022
      Udugama B; Jayasinghe D; Saadat H; Ignjatovic A; Parameswaran S, 2022, 'A Power to Pulse Width Modulation Sensor for Remote Power Analysis Attacks', Iacr Transactions on Cryptographic Hardware and Embedded Systems, 2022, pp. 589 - 613, http://dx.doi.org/10.46586/tches.v2022.i4.589-613
      Journal articles | 2021
      Gamaarachchi H; Samarakoon H; Jenner S; Ferguson J; Amos T; Hammond J; Saadat H; Smith M; Parameswaran S; Deveson I, 2021, 'SLOW5: a new file format enables massive acceleration of nanopore sequencing data analysis', , http://dx.doi.org/10.1101/2021.06.29.450255
      Journal articles | 2021
      Gamaarachchi H; Samarakoon H; Jenner S; Ferguson J; Amos T; Hammond J; Saadat H; Smith M; Parameswaran S; Deveson I, 2021, 'SLOW5: a new file format enables massive acceleration of nanopore sequencing data analysis', , http://dx.doi.org/10.21203/rs.3.rs-668517/v1
      Journal articles | 2021
      Hussain S; Guo H; Li T; Saadat H; Parameswaran S, 2021, 'COPS: A complete oblivious processing system', Microprocessors and Microsystems, 85, http://dx.doi.org/10.1016/j.micpro.2021.104295
      Journal articles | 2021
      Jayasinghe D; Ignjatovic A; Parameswaran S, 2021, 'UCloD: Small Clock Delays to Mitigate Remote Power Analysis Attacks', IEEE Access, 9, pp. 108411 - 108425, http://dx.doi.org/10.1109/ACCESS.2021.3100618
      Journal articles | 2021
      Jayasinghe D; Ignjatovic A; Ragel R; Ambrose JA; Parameswaran S, 2021, 'QuadSeal: Quadruple Balancing to Mitigate Power Analysis Attacks with Variability Effects and Electromagnetic Fault Injection Attacks', ACM Transactions on Design Automation of Electronic Systems, 26, http://dx.doi.org/10.1145/3443706
      Journal articles | 2021
      Udugama B; Jayasinghe D; Saadat H; Ignjatovic A; Parameswaran S, 2021, 'VITI: A Tiny Self-Calibrating Sensor for Power-Variation Measurement in FPGAs', Iacr Transactions on Cryptographic Hardware and Embedded Systems, 2022, pp. 657 - 678, http://dx.doi.org/10.46586/tches.v2022.i1.657-678
      Journal articles | 2020
      Bayat A; Deshpande NP; Wilkins MR; Parameswaran S, 2020, 'Fast Short Read De-Novo Assembly Using Overlap-Layout-Consensus Approach', IEEE ACM Transactions on Computational Biology and Bioinformatics, 17, pp. 334 - 338, http://dx.doi.org/10.1109/TCBB.2018.2875479
      Journal articles | 2020
      Gamaarachchi H; Bayat A; Gaeta B; Parameswaran S, 2020, 'Cache Friendly Optimisation of de Bruijn Graph Based Local Re-Assembly in Variant Calling', IEEE ACM Transactions on Computational Biology and Bioinformatics, 17, pp. 1125 - 1133, http://dx.doi.org/10.1109/TCBB.2018.2881975
      Journal articles | 2020
      Gamaarachchi H; Lam CW; Jayatilaka G; Samarakoon H; Simpson JT; Smith MA; Parameswaran S, 2020, 'GPU accelerated adaptive banded event alignment for rapid comparative nanopore signal analysis', BMC Bioinformatics, 21, http://dx.doi.org/10.1186/s12859-020-03697-x
      Journal articles | 2020
      Malekpour A; Ragel R; Tuo LI; Javaid H; Ignjatovic A; Parameswaran S, 2020, 'Hardware Trojan mitigation in pipelined MPSoCs', ACM Transactions on Design Automation of Electronic Systems, 25, http://dx.doi.org/10.1145/3365578
      Journal articles | 2019
      Bayat A; Gaëta B; Ignjatovic A; Parameswaran S, 2019, 'Pairwise alignment of nucleotide sequences using maximal exact matches', BMC Bioinformatics, 20, pp. 261, http://dx.doi.org/10.1186/s12859-019-2827-0
      Journal articles | 2019
      Gamaarachchi H; Lam CW; Jayatilaka G; Samarakoon H; Simpson J; Smith M; Parameswaran S, 2019, 'GPU Accelerated Adaptive Banded Event Alignment for Rapid Comparative Nanopore Signal Analysis', bioRxiv, http://dx.doi.org/10.1101/756122
      Journal articles | 2019
      Gamaarachchi H; Parameswaran S; Smith MA, 2019, 'Featherweight long read alignment using partitioned reference indexes', Scientific Reports, 9, pp. 4318, http://dx.doi.org/10.1038/s41598-019-40739-8
      Journal articles | 2018
      Gamaarachchi H; Parameswaran S; Smith M, 2018, 'Featherweight long read alignment using partitioned reference indexes', BIORXIV, http://dx.doi.org/10.1101/386847
      Journal articles | 2018
      Parameswaran S; Iris Bahar R; Pan DZ, 2018, 'Conference Reports: Report on the 2017 International Conference on Computer-Aided Design (ICCAD)', IEEE Design and Test, 35, pp. 101 - 102, http://dx.doi.org/10.1109/MDAT.2018.2799991
      Journal articles | 2018
      Saadat H; Bokhari H; Parameswaran S, 2018, 'Minimally biased multipliers for approximate integer and floating-point multiplication', IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 37, pp. 2623 - 2635, http://dx.doi.org/10.1109/TCAD.2018.2857262
      Journal articles | 2017
      Aluthwala PD; Weste N; Adams A; Lehmann T; Parameswaran S, 2017, 'Partial dynamic element matching technique for digital-to-analog converters used for digital harmonic-cancelling sine-wave synthesis', IEEE Transactions on Circuits and Systems I Regular Papers, 64, pp. 296 - 309, http://dx.doi.org/10.1109/TCSI.2016.2613938
      Journal articles | 2017
      Bayat A; Gaëta B; Ignjatovic A; Parameswaran S, 2017, 'Improved VCF normalization for accurate VCF comparison.', Bioinformatics, 33, pp. 964 - 970, http://dx.doi.org/10.1093/bioinformatics/btw748
      Journal articles | 2017
      Li T; Ambrose JA; Ragel R; Parameswaran S, 2017, 'Processor design for soft errors: Challenges and state of the art', ACM Computing Surveys, 49, http://dx.doi.org/10.1145/2996357
      Journal articles | 2017
      Li T; Shafique M; Ambrose JA; Henkel J; Parameswaran S, 2017, 'Fine-Grained Checkpoint Recovery for Application-Specific Instruction-Set Processors', IEEE Transactions on Computers, 66, pp. 647 - 660, http://dx.doi.org/10.1109/TC.2016.2606378
      Journal articles | 2017
      Liu T; Guo H; Parameswaran S; Hu SX, 2017, 'iCETD: An improved tag generation design for memory data authentication in embedded processor systems', Integration the VLSI Journal, 56, pp. 96 - 104, http://dx.doi.org/10.1016/j.vlsi.2016.10.006
      Journal articles | 2016
      Nawinne I; Javaid H; Ragel R; Parameswaran S, 2016, 'Switchable cache: Utilising dark silicon for application specific cache optimisations', Iet Computers and Digital Techniques, 10, pp. 157 - 164, http://dx.doi.org/10.1049/iet-cdt.2015.0114
      Journal articles | 2016
      Parameswaran S, 2016, 'Editorial Introduction of New Editor-in-Chief and Associate Editors', IEEE Embedded Systems Letters, 8, pp. 1, http://dx.doi.org/10.1109/LES.2016.2532418
      Journal articles | 2015
      Nawinne I; Javaid H; Ragel R; Radhakrishnan S; Parameswaran S, 2015, 'Exploring Multilevel Cache Hierarchies in Application Specific MPSoCs', IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 34, pp. 1991 - 2003, http://dx.doi.org/10.1109/TCAD.2015.2445736
      Journal articles | 2015
      Ragel RG; Ambrose JA; Parameswaran S, 2015, 'SecureD: A Secure Dual Core Embedded Processor', SecureD: A Secure Dual Core Embedded Processor, http://arxiv.org/abs/1511.01946v1
      Journal articles | 2014
      Javaid H; Ignjatovic A; Parameswaran S, 2014, 'Performance estimation of pipelined multiprocessor system-on-chips (MPSoCs)', IEEE Transactions on Parallel and Distributed Systems, 25, pp. 2159 - 2168, http://dx.doi.org/10.1109/TPDS.2013.268
      Journal articles | 2014
      Javaid H; Shafique M; Henkel J; Parameswaran S, 2014, 'Energy-efficient adaptive pipelined MPSoCs for multimedia applications', IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 33, pp. 663 - 676, http://dx.doi.org/10.1109/TCAD.2014.2298196
      Journal articles | 2012
      Ambrose JA; Aldon N; Ignjatovic A; Parameswaran S, 2012, 'Differential Power Analysis in AES: A Crypto Anatomy', IJEI: International Journal of Engineering and Industries, 2, pp. 118 - 130, http://www.aicit.org/ijei/global/paper_detail.html?jname=IJEI&q=46
      Journal articles | 2012
      Ambrose JA; Ragel RG; Parameswaran S, 2012, 'Randomized Instruction Injection to Counter Power Analysis Attacks', ACM Transactions on Embedded Computing Systems (TECS), 11, pp. 28, http://dl.acm.org/citation.cfm?id=2345782
      Journal articles | 2011
      Ambrose JA; Ragel RG; Parameswaran S; Ignjatovic A, 2011, 'Multiprocessor information concealment architecture to prevent power analysis-based side channel attacks', IET Computers and Digital Techniques, 5, pp. 1 - 15, http://dx.doi.org/10.1049/iet-cdt.2009.0097
      Journal articles | 2011
      Patel K; Parameswaran S; Ragel RG, 2011, 'Architectural frameworks for security and reliability of MPSoCs', IEEE Transactions on Very Large Scale Integration (Vlsi) Systems, 19, pp. 1641 - 1654, http://dx.doi.org/10.1109/TVLSI.2010.2053856
      Journal articles | 2011
      Ragel RG; Parameswaran S, 2011, 'A hybrid hardware-software technique to improve reliability in embedded processors', ACM Transactions on Embedded Computing Systems (TECS), 10, pp. Article number: 36, http://dx.doi.org/10.1145/1952522.1952529
      Journal articles | 2010
      Henkel J; Parameswaran S, 2010, 'CASES 2009 guest editor's introduction', Design Automation for Embedded Systems, 14, pp. 285 - 286, http://dx.doi.org/10.1007/s10617-010-9060-4
      Journal articles | 2010
      Javaid H; He X; Ignjatovic A; Parameswaran S, 2010, 'Optimal synthesis of latency and throughput constrained pipelined MPSoCs targeting streaming applications', 2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2010, pp. 75 - 84
      Journal articles | 2010
      Javaid H; Ignjatovic A; Parameswaran S, 2010, 'Rapid Design Space Exploration of Application Specific Heterogeneous Pipelined Multiprocessor Systems', IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 29, pp. 1777 - 1789, http://dx.doi.org/10.1109/TCAD.2010.2061353
      Journal articles | 2009
      Avnit K; D Silva V; Sowmya A; Ramesh S; Parameswaran S, 2009, 'Provably correct on-chip communication: A formal approach to automatic protocol converter synthesis', ACM Transactions on Design Automation of Electronic Systems, 14
      Journal articles | 2009
      Chong Y; Parameswaran S, 2009, 'Custom Floating-Point Unit Generation for Embedded Systems', IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28, pp. 638 - 650
      Journal articles | 2009
      Chong YJ; Parameswaran S, 2009, 'Custom floating-point unit generation for embedded systems', IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 28, pp. 638 - 650
      Journal articles | 2009
      Radhakrishnan S; Guo HA; Parameswaran S; Ignjatovic A, 2009, 'HMP-ASIP`s: heterogeneous multi-pipeline application-specific instruction-set processors', IET Computers and Digital Techniques, 3, pp. 94 - 108
      Journal articles | 2008
      Parameswaran S; Wolf T, 2008, 'Embedded systems security - an overview', Design Automation for Embedded Systems, 12, pp. 173 - 183
      Journal articles | 2008
      Peddersen JM; Parameswaran S, 2008, 'Energy driven application self-adaptation at run-time', Journal of Computers (JCP), 3, pp. 14 - 24, http://dx.doi.org/10.4304/jcp.3.3.14-24
      Journal articles | 2008
      Peddersen JM; Parameswaran S, 2008, 'Low-impact processor for dynamic runtime power management', IEEE Design and Test of Computers, 25, pp. 52 - 62, http://dx.doi.org/10.1109/MDT.2008.23
      Journal articles | 2008
      Shee SL; Erdos A; Parameswaran S, 2008, 'Architectural exploration of heterogeneous multiprocessor systems for JPEG', International Journal of Parallel Programming, 36, pp. 140 - 162, http://dx.doi.org/10.1007/s10766-007-0040-7
      Journal articles | 2008
      Wolf T; Parameswaran S, 2008, 'Guest editorial for special issue on embedded system security', Design Automation for Embedded Systems, 12, pp. 171 - 172
      Journal articles | 2007
      Lu IS; Weste N; Parameswaran S, 2007, 'A power-efficient 5.6-GHz process-compensated CMOS frequency divider', IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 54, pp. 323 - 327, http://dx.doi.org/10.1109/TCSII.2006.889741
      Journal articles | 2007
      Parameswaran S; Henkel J; Cheung N, 2007, 'Instruction matching and modeling', , pp. 257 - 280, http://dx.doi.org/10.1016/B978-012369526-0/50012-7
      Journal articles | 2007
      Peddersen J; Parameswaran S, 2007, 'Low-Impact processor for dynamic runtime power management', IEEE Design & Test of Computers, 24, pp. x4 - x4, http://dx.doi.org/10.1109/mdt.2007.4343581
      Journal articles | 2006
      Janapsatya AG; Ignjatovic A; Parameswaran S, 2006, 'Exploiting statistical information for implementation of instruction scratchpad memory in embedded systems', IEEE Transactions on Very Large Scale Integration (Vlsi) Systems, 14, pp. 816 - 829
      Journal articles | 2005
      Parameswaran S; Henkel J, 2005, 'Instruction code mapping for performance increase and energy reduction in embedded computer systems', IEEE Transactions on Very Large Scale Integration (Vlsi) Systems, 13, pp. 498 - 502
      Journal articles | 2004
      Janapsatya AG; Henkel J; Parameswaran S, 2004, 'REMcode: relocating embedded code for improving system efficiency', IEE Proceedings-Computers and Digital Techniques, 151, pp. 457 - 465
      Journal articles | 2004
      Sachdev PS, 2004, 'Foreword', Sensorium - A neuroscience journal for Australasian clinicians, Issue 5, pp. 1 - 1
      Journal articles | 2001
      Parameswaran S; Henkel J, 2001, 'I-CoPES: Fast instruction code placement for embedded systems to improve performance and energy efficiency', IEEE ACM International Conference on Computer Aided Design Digest of Technical Papers, pp. 635 - 641, http://dx.doi.org/10.1109/ICCAD.2001.968728
      Journal articles | 2001
      Rae A; Parameswaran S, 2001, 'Synthesising application-specific heterogeneous multiprocessors using differential evolution', IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E84A, pp. 3125 - 3131, https://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000172877000020&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=891bb5ab6ba270e68a29b250adbe88d1
      Journal articles | 2001
      Rae A; Parameswaran S, 2001, 'Synthesising application-specific heterogeneous multiprocessors using differential evolution', IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, E84-A, pp. 3125 - 3131
      Journal articles | 2001
      Rae A; Parameswaran S, 2001, 'Voltage reduction of application-specific heterogeneous multiprocessor systems for power minimisation', IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E84A, pp. 2296 - 2302, https://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000171700800027&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=891bb5ab6ba270e68a29b250adbe88d1
      Journal articles | 2001
      Rae A; Parameswaran S, 2001, 'Voltage reduction of application-specific heterogeneous multiprocessor systems for power minimisation', IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, E84-A, pp. 2296 - 2302
      Journal articles | 2000
      Parameswaran S; Parkinson MF; Bartlett P, 2000, 'Profiling in the ASP codesign environment', Journal of Systems Architecture, 46, pp. 1263 - 1274, http://dx.doi.org/10.1016/S1383-7621(00)00016-3
      Journal articles | 1999
      Kia SM; Parameswaran S, 1999, 'Self-checking synchronous controller design', IEE Proceedings Computers and Digital Techniques, 146, pp. 9 - 12, http://dx.doi.org/10.1049/ip-cdt:19990243
      Journal articles | 1998
      Guo H; Paramewaran S, 1998, 'Unrolling loops with indeterminate loop counts in system level pipelines', Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC, pp. 99 - 104
      Journal articles | 1998
      Kia SM; Parameswaran S, 1998, 'Designs for self checking flip-flops', IEE Proceedings Computers and Digital Techniques, 145, pp. 81 - 88, http://dx.doi.org/10.1049/ip-cdt:19981907
      Journal articles | 1998
      Parameswaran S; Guo H, 1998, 'Power reduction in pipelines', Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC, pp. 545 - 550
      Journal articles | 1998
      Parameswaran S, 1998, 'HW-SW co-synthesis: The present and the future', Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC, pp. 19 - 22
      Journal articles | 1995
      Jha P; Parameswaran S; Dutt N, 1995, 'Reclocking controllers for minimum execution time', IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E78A, pp. 1715 - 1721, https://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:A1995TM34400016&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=891bb5ab6ba270e68a29b250adbe88d1
      Journal articles | 1995
      Jha P; Parameswaran S; Dutt N, 1995, 'Reclocking controllers for minimum execution time', IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, E78-A, pp. 1715 - 1721
    • Conference Papers | 2025
      Udugama B; Jayasinghe D; Saadat H; Ignjatovic A; Parameswaran S, 2025, 'A Novel Covert Timing Channel for Cloud FPGAs', in Proceedings Design Automation Conference, http://dx.doi.org/10.1109/DAC63849.2025.11133099
      Conference Papers | 2024
      Bhargavi MB; Sai Harshith GS; Parameswaran S; Soumya J, 2024, 'Optimizing LU Decomposition with RISC-V Based Hardware Acceleration', in Proceedings of IEEE Computer Society Annual Symposium on VLSI Isvlsi, pp. 210 - 215, http://dx.doi.org/10.1109/ISVLSI61997.2024.00047
      Conference Papers | 2024
      Bhargavi MB; Siddharth Rokkam S; Parameswaran S; Soumya J, 2024, 'Automated Design and Configuration of RISC-V based NoC-MPSoC Framework on FPGA', in 2024 28th International Symposium on VLSI Design and Test Vdat 2024, http://dx.doi.org/10.1109/VDAT63601.2024.10705744
      Conference Papers | 2024
      Gong J; Saadat H; Javaid H; Gamaarachchi H; Taubman D; Parameswaran S, 2024, 'SEA: Sign-Separated Accumulation Scheme for Resource-Efficient DNN Accelerators', in Proceedings Design Automation and Test in Europe Date
      Conference Papers | 2024
      Liyanage K; Gamaarachchi H; Saadat H; Li T; Samarakoon H; Parameswaran S, 2024, 'Accelerating Chaining in Genomic Analysis Using RISC- V Custom Instructions', in Proceedings Design Automation and Test in Europe Date
      Preprints | 2024
      Samarakoon H; Liyanage K; Ferguson J; Parameswaran S; Gamaarachchi H; Deveson I, 2024, Interactive visualisation of raw nanopore signal data with Squigualiser, http://dx.doi.org/10.1101/2024.02.19.581111
      Preprints | 2024
      Samarakoon H; Wan YK; Parameswaran S; Göke J; Gamaarachchi H; Deveson I, 2024, Leveraging Basecaller’s Move Table to Generate a Lightweight k-mer Model, http://dx.doi.org/10.1101/2024.06.30.601452
      Conference Papers | 2024
      Udugama B; Jayasinghe D; Parameswaran S, 2024, 'Sensors for Remote Power Attacks: New Developments and Challenges', in Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC, pp. 333 - 340, http://dx.doi.org/10.1109/ASP-DAC58780.2024.10473890
      Conference Papers | 2023
      Gamaarachchi H; Liyanage K; Parameswaran S, 2023, 'Invited: Algorithms and Architectures for Accelerating Long Read Sequence Analysis', in Proceedings Design Automation Conference, http://dx.doi.org/10.1109/DAC56929.2023.10247772
      Conference Papers | 2023
      Jayasinghe D; Udugama B; Parameswaran S, 2023, 'FPGA Based Countermeasures against Side Channel Attacks on Block Ciphers', in Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC, pp. 365 - 371, http://dx.doi.org/10.1145/3566097.3568353
      Preprints | 2023
      Liyanage K; Samarakoon H; Parameswaran S; Gamaarachchi H, 2023, minimap2-fpga: Integrating hardware-accelerated chaining for efficient end-to-end long-read sequence mapping, http://dx.doi.org/10.1101/2023.05.30.542681
      Conference Papers | 2022
      Dow HK; Li T; Parameswaran S, 2022, 'HWST128: Complete Memory Safety Accelerator on RISC-V with Metadata Compression', in Proceedings Design Automation Conference, pp. 709 - 714, http://dx.doi.org/10.1145/3489517.3530548
      Preprints | 2022
      Gong J; Saadat H; Gamaarachchi H; Javaid H; Hu XS; Parameswaran S, 2022, ApproxTrain: Fast Simulation of Approximate Multipliers for DNN Training and Inference, http://dx.doi.org/10.48550/arxiv.2209.04161
      Conference Papers | 2022
      Li T; Parameswaran S, 2022, 'FaSe: Fast Selective Flushing to Mitigate Contention-based Cache Timing Attacks', in Proceedings Design Automation Conference, pp. 541 - 546, http://dx.doi.org/10.1145/3489517.3530491
      Preprints | 2022
      Samarakoon H; Ferguson J; Jenner S; Amos T; Parameswaran S; Gamaarachchi H; Deveson I, 2022, Flexible and efficient handling of nanopore sequencing signal data with slow5tools, http://dx.doi.org/10.1101/2022.06.19.496732
      Preprints | 2022
      Shih PJ; Saadat H; Parameswaran S; Gamaarachchi H, 2022, Efficient Real-Time Selective Genome Sequencing on Resource-Constrained Devices, http://arxiv.org/abs/2211.07340v1
      Conference Papers | 2021
      Dow HK; Li T; Miles W; Parameswaran S, 2021, 'SHORE: Hardware/Software Method for Memory Safety Acceleration on RISC-V', in Proceedings Design Automation Conference, pp. 289 - 294, http://dx.doi.org/10.1109/DAC18074.2021.9586293
      Preprints | 2021
      Gamaarachchi H; Samarakoon H; Jenner S; Ferguson J; Amos T; Hammond J; Saadat H; Smith M; Parameswaran S; Deveson I, 2021, SLOW5: a new file format enables massive acceleration of nanopore sequencing data analysis, http://dx.doi.org/10.1101/2021.06.29.450255
      Conference Papers | 2021
      Zervakis G; Saadat H; Mrouch H; Gerstlauer A; Parameswaran S; Henkel J, 2021, 'Approximate Computing for ML: State-of-the-art, Challenges and Visions', in Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC, pp. 189 - 196, http://dx.doi.org/10.1145/3394885.3431632
      Conference Papers | 2020
      Abid F; Jayasinghe D; Somsavaddy S; Parameswaran S, 2020, 'LFTSM: Lightweight and Fully Testable SEU Mitigation System for Xilinx Processor-Based SoCs', in Proceedings 30th International Conference on Field Programmable Logic and Applications Fpl 2020, pp. 162 - 168, http://dx.doi.org/10.1109/FPL50879.2020.00036
      Preprints | 2020
      Bayat A; Gamaarachchi H; Deshpande N; Wilkins M; Parameswaran S, 2020, Methods for De-novo Genome Assembly, http://dx.doi.org/10.20944/preprints202006.0324.v1
      Conference Papers | 2020
      Gnanasambandapillai V; Peddersen J; Ragel R; Parameswaran S, 2020, 'FINDER: Find Efficient Parallel Instructions for ASIPs to Improve Performance of Large Applications', in IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, pp. 3577 - 3588, http://dx.doi.org/10.1109/TCAD.2020.3012211
      Conference Papers | 2020
      Laguna AF; Gamaarachchi H; Yin X; Niemier M; Parameswaran S; Hu XS, 2020, 'Seed-and-Vote based In-Memory Accelerator for DNA Read Mapping', in IEEE ACM International Conference on Computer Aided Design Digest of Technical Papers Iccad, http://dx.doi.org/10.1145/3400302.3415651
      Preprints | 2020
      Li T; Hopkins B; Parameswaran S, 2020, SIMF: Single-Instruction Multiple-Flush Mechanism for Processor Temporal Isolation, http://arxiv.org/abs/2011.10249v2
      Conference Papers | 2020
      Saadat H; Javaid H; Ignjatovic A; Parameswaran S, 2020, 'REALM: Reduced-Error Approximate Log-based Integer Multiplier', in Proceedings of the 2020 Design Automation and Test in Europe Conference and Exhibition Date 2020, pp. 1366 - 1371, http://dx.doi.org/10.23919/DATE48585.2020.9116315
      Conference Papers | 2020
      Saadat H; Javaid H; Ignjatovic A; Parameswaran S, 2020, 'WEID: Worst-case Error Improvement in Approximate Dividers', in Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC, Institute of Electrical and Electronics Engineers (IEEE), PEOPLES R CHINA, Beijing, pp. 593 - 598, presented at 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), PEOPLES R CHINA, Beijing, 13 January 2020 - 16 January 2020, http://dx.doi.org/10.1109/ASP-DAC47756.2020.9045504
      Conference Papers | 2020
      Saadat H; Li T; Javaid H; Parameswaran S, 2020, 'A sub-range error characterization based selection methodology for approximate arithmetic units', in Proceedings 33rd International Conference on VLSI Design Vlsid 2020 Held Concurrently with 19th International Conference on Embedded Systems, pp. 84 - 89, http://dx.doi.org/10.1109/VLSID49098.2020.00032
      Preprints | 2019
      Gamaarachchi H; Lam CW; Jayatilaka G; Samarakoon H; Simpson J; Smith M; Parameswaran S, 2019, GPU Accelerated Adaptive Banded Event Alignment for Rapid Comparative Nanopore Signal Analysis, http://dx.doi.org/10.1101/756122
      Conference Papers | 2019
      Jayasinghe D; Ignjatovic A; Parameswaran S, 2019, 'RFTC: Runtime frequency tuning countermeasure using FPGA dynamic reconfiguration to mitigate power analysis attacks', in Proceedings Design Automation Conference, http://dx.doi.org/10.1145/3316781.3317899
      Conference Papers | 2019
      Jayasinghe D; Ignjatovic A; Parameswaran S, 2019, 'SCRIP: Secure random clock execution on soft processor systems to mitigate power-based side channel attacks', in IEEE ACM International Conference on Computer Aided Design Digest of Technical Papers Iccad, http://dx.doi.org/10.1109/ICCAD45719.2019.8942112
      Conference Papers | 2019
      Malekpour A; Ragel R; Murphy D; Ignjatovic A; Parameswaran S, 2019, 'Hardware Trojan Detection and Recovery in MPSoCs via On-line Application Specific Testing', in Proceedings 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems Ddecs 2019, http://dx.doi.org/10.1109/DDECS.2019.8724649
      Conference Papers | 2019
      Prasad Mohanty R; Gamaarachchi H; Lambert A; Parameswaran S, 2019, 'Swaram: Portable energy and cost efficient embedded system for genomic processing', in ACM Transactions on Embedded Computing Systems, http://dx.doi.org/10.1145/3358211
      Conference Papers | 2019
      Saadat H; Javaid H; Parameswaran S, 2019, 'Approximate integer and floating-point dividers with near-zero error bias', in Proceedings Design Automation Conference, http://dx.doi.org/10.1145/3316781.3317773
      Preprints | 2018
      Gamaarachchi H; Parameswaran S; Smith M, 2018, Featherweight long read alignment using partitioned reference indexes, http://dx.doi.org/10.1101/386847
      Conference Papers | 2018
      Gnanasambandapillai V; Bayat A; Parameswaran S, 2018, 'MESGA: An MPSoC based embedded system solution for short read genome alignment', in Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC, pp. 52 - 57, http://dx.doi.org/10.1109/ASPDAC.2018.8297282
      Conference Papers | 2018
      Hussain M; Malekpour A; Guo H; Parameswaran S, 2018, 'EETD: An energy efficient design for runtime hardware trojan detection in untrusted network-on-chip', in Proceedings of IEEE Computer Society Annual Symposium on VLSI Isvlsi, pp. 345 - 350, http://dx.doi.org/10.1109/ISVLSI.2018.00070
      Conference Papers | 2018
      Irena F; Murphy D; Parameswaran S, 2018, 'CryptoBlaze: A partially homomorphic processor with multiple instructions and non-deterministic encryption support', in Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC, pp. 702 - 708, http://dx.doi.org/10.1109/ASPDAC.2018.8297404
      Conference Papers | 2018
      Parameswaran S; Kishore R, 2018, 'Social support in online health communities: A social-network approach', in SIGMIS Cpr 2018 Proceedings of the 2018 ACM SIGMIS Conference on Computers and People Research, pp. 93 - 94, http://dx.doi.org/10.1145/3209626.3209725
      Conference Papers | 2018
      Wang X; Bagul DM; Parameswaran S; Kishore R, 2018, 'Does Online Social Support Work in Stigmatized Chronic Diseases? A Study of the Impacts of Different Facets of Informational and Emotional Support on Self-Care Behavior in an HIV Online Forum', in ICIS 2017: Transforming Society with Digital Innovation
      Conference Papers | 2017
      Ignjatovic A; Jayasinghe D; Parameswaran S, 2017, 'NORA: Algorithmic Balancing without Pre-charge to Thwart Power Analysis Attacks', in VLSI Design 2017, Hyderabad, India, presented at 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, VLSID 2017, Hyderabad, India, 07 January 2017 - 11 January 2017
      Conference Papers | 2017
      Khinda R; Parameswaran S; Mitra G; Lin X; Verni C; Kishore R; Billittier A, 2017, 'Use of gamified social media with home telemonitoring for patient self-management in poorly controlled medicaid diabetics: A pilot study of health outcomes, social influences, and habit formation', in SIGMIS Cpr 2017 Proceedings of the 2017 ACM SIGMIS Conference on Computers and People Research, pp. 171 - 172, http://dx.doi.org/10.1145/3084381.3084417
      Conference Papers | 2017
      Malekpour A; Ragel R; Ignjatovic A; Parameswaran S, 2017, 'DoSGuard: Protecting pipelined MPSoCs against hardware Trojan based DoS attacks', in Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors, Seattle, WA, USA, pp. 45 - 52, presented at 2017 IEEE 28th International Conference on Application-specific Systems, Architectures and Processors (ASAP), Seattle, WA, USA, 10 July 2017 - 12 July 2017, http://dx.doi.org/10.1109/ASAP.2017.7995258
      Conference Papers | 2017
      Malekpour A; Ragel R; Ignjatovic A; Parameswaran S, 2017, 'TrojanGuard: Simple and Effective Hardware Trojan Mitigation Techniques for Pipelined MPSoCs', in Proceedings Design Automation Conference, http://dx.doi.org/10.1145/3061639.3062336
      Conference Papers | 2017
      Parameswaran S; Kishore R, 2017, 'A social presence model of task performance: A meta-analytic structural equation model', in Amcis 2017 America S Conference on Information Systems A Tradition of Innovation
      Conference Papers | 2017
      Parameswaran S, 2017, 'Social presence in social media: Persuasion, design and discourse', in SIGMIS Cpr 2017 Proceedings of the 2017 ACM SIGMIS Conference on Computers and People Research, pp. 205 - 206, http://dx.doi.org/10.1145/3084381.3084428
      Conference Papers | 2017
      Saadat H; Parameswaran S, 2017, 'Special session: Hardware approximate computing: How, why, when and where?', in Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion, CASES 2017, Seoul, Republic of Korea, presented at 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion, Seoul, Republic of Korea, 15 October 2017 - 20 October 2017, http://dx.doi.org/10.1145/3125501.3125518
      Conference Papers | 2016
      Aluthwala P; Weste N; Adams A; Lehmann T; Parameswaran S, 2016, 'The effect of amplitude resolution and mismatch on a digital-to-analog converter used for digital harmonic-cancelling sine-wave synthesis', in Proceedings - IEEE International Symposium on Circuits and Systems, IEEE, Montreal, CANADA, pp. 2018 - 2021, presented at IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, CANADA, 22 May 2016 - 25 May 2016, http://dx.doi.org/10.1109/ISCAS.2016.7538973
      Conference Papers | 2016
      Jayasinghe JA; Shivam Bashin ; Parameswaran S; Ignjatovic A, 2016, 'Does It Sound as It Claims: A Detailed Side-Channel Security Analysis of QuadSeal Countermeasure', Como, Italy, presented at ACM International Conference on Computing Frontiers 2016, Como, Italy, 16 May 2016 - 18 May 2016, http://dx.doi.org/10.1145/2903150.2911709
      Conference Papers | 2016
      Li T; Ambrose JA; Parameswaran S, 2016, 'RECORD: Reducing register traffic for checkpointing in embedded processors', in Proceedings of the 2016 Design Automation and Test in Europe Conference and Exhibition Date 2016, pp. 582 - 587, http://dx.doi.org/10.3850/9783981537079_0191
      Conference Papers | 2016
      Liu T; Guo H; Parameswaran S; Hu XS, 2016, 'Improving tag generation for memory data authentication in embedded processor systems', in Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC, pp. 50 - 55, http://dx.doi.org/10.1109/ASPDAC.2016.7427988
      Conference Papers | 2016
      Nemati N; Reed MC; Parameswaran S; Fant K, 2016, 'Self-Timed Automatic Test Pattern Generation for Null Convention Logic', in 2016 IEEE 59TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), IEEE, U ARAB EMIRATES, Abu Dhabi, pp. 369 - 372, presented at 59th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), U ARAB EMIRATES, Abu Dhabi, 16 October 2016 - 19 October 2016, https://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000404343800093&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=891bb5ab6ba270e68a29b250adbe88d1
      Conference Papers | 2016
      Nemati N; Reed MC; Parameswaran S; Fant K, 2016, 'Self-Timed automatic test pattern generation for null convention logic', in Midwest Symposium on Circuits and Systems, Abu Dhabi, United Arab Emirates, presented at 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS), Abu Dhabi, United Arab Emirates, 16 October 2016 - 19 October 2016, http://dx.doi.org/10.1109/MWSCAS.2016.7870032
      Conference Papers | 2015
      Aluthwala PD; Lehmann T; Parameswaran S, 2015, 'Design of a Digital Harmonic-Cancelling Sine-Wave Synthesizer with 100 MHz Output Frequency, 43.5 dB SFDR, and 2.26 mW Power', in Proceedings - IEEE International Symposium on Circuits and Systems, Institute of Electrical and Electronics Engineers, Lisbon, Portugal, presented at International Symposium on Circuits and Systems, Lisbon, Portugal, 24 May 2015 - 27 May 2015
      Conference Papers | 2015
      Ambrose JA; Higgins N; Chakravarthy M; Garg S; Li T; Murphy D; Ignjatovic A; Parameswaran S, 2015, 'ARCHER: Communication-based predictive architecture selection for application specific multiprocessor Systems-on-Chip', in Proceedings IEEE International Symposium on Circuits and Systems, pp. 413 - 416, http://dx.doi.org/10.1109/ISCAS.2015.7168658
      Conference Papers | 2015
      Ambrose JA; Li T; Murphy D; Gargg S; Higgins N; Parameswaran S, 2015, 'ARGUS: A Framework for Rapid Design and Prototype of Heterogeneous Multicore Systems in FPGA', in Proceedings of the IEEE International Conference on VLSI Design, pp. 29 - 34, http://dx.doi.org/10.1109/VLSID.2015.10
      Conference Papers | 2015
      Ambrose JA; Ragel RG; Jayasinghe D; Li T; Parameswaran S, 2015, 'Side channel attacks in embedded systems: A tale of hostilities and deterrence', in Proceedings International Symposium on Quality Electronic Design Isqed, pp. 452 - 459, http://dx.doi.org/10.1109/ISQED.2015.7085468
      Conference Papers | 2015
      Ambrose JA; Yachide Y; Batra K; Peddersen JMD; Parameswaran S, 2015, 'Sequential C-code to Distributed Pipelined Heterogeneous MPSoC Synthesis for Streaming Applications', in Proceedings of the 33rd IEEE International Conference on Computer Design Iccd 2015, Institute of Electrical and Electronics Engineers (IEEE), New York, NY, USA, pp. 216 - 223, presented at IEEE International Conference on Computer Design (ICCD), New York, NY, USA, 18 October 2015 - 21 October 2015, http://dx.doi.org/10.1109/ICCD.2015.7357106
      Conference Papers | 2015
      Bokhari H; Javaid H; Shafique M; Henkel J; Parameswaran S, 2015, 'Malleable NoC: Dark silicon inspired adaptable Network-on-Chip', in Proceedings Design Automation and Test in Europe Date, pp. 1245 - 1248, http://dx.doi.org/10.7873/date.2015.0694
      Conference Papers | 2015
      Bokhari H; Javaid H; Shafique M; Henkel J; Parameswaran S, 2015, 'SuperNet: Multimode interconnect architecture for manycore chIPs', in Proceedings Design Automation Conference, http://dx.doi.org/10.1145/2744769.2744912
      Conference Papers | 2015
      Bokhari H; Parameswaran SRI; Shafique M; Garg S; Khan MUK; Khdr H; Kriebel F; Ogras UY; Henkel J, 2015, 'Dark Silicon: From Computation to Communication', Vancouver, Canada, presented at 9th International Symposium on Networks-on-Chip (NoC'15), Vancouver, Canada, 28 September 2015 - 30 September 2015, http://dx.doi.org/10.1145/2786572.2788707
      Preprints | 2015
      Haque MS; Peddersen J; Janapsatya A; Parameswaran S, 2015, DEW: A Fast Level 1 Cache Simulation Approach for Embedded Processors with FIFO Replacement Policy, http://dx.doi.org/10.1109/DATE.2010.5457153
      Preprints | 2015
      Haque MS; Peddersen J; Parameswaran S, 2015, CIPARSim: Cache Intersection Property Assisted Rapid Single-pass FIFO Cache Simulation Technique, http://dx.doi.org/10.1109/ICCAD.2011.6105316
      Conference Papers | 2015
      Jayasinghe D; Ignjatovic A; Ambrose JA; Ragel R; Parameswaran S, 2015, 'QuadSeal: Quadruple algorithmic symmetrizing countermeasure against power based side-channel attacks', in 2015 International Conference on Compilers Architecture and Synthesis for Embedded Systems Cases 2015, pp. 21 - 30, http://dx.doi.org/10.1109/CASES.2015.7324539
      Preprints | 2015
      Ragel RG; Ambrose JA; Parameswaran S, 2015, SecureD: A Secure Dual Core Embedded Processor, http://arxiv.org/abs/1511.01946v1
      Conference Papers | 2015
      Schneider JL; Pedersen J; Parameswaran S, 2015, 'Speeding Up Single Pass Simulation of PLRUt Caches', presented at 2015 20th Asia and South Pacific Design Automation Conference, 19 January 2015 - 22 January 2015
      Conference Papers | 2015
      Shwe S; Batra K; Yachide Y; Peddersen JM; Parameswaran S, 2015, 'RAPITIMATE: Rapid performance estimation of pipelined processing systems containing shared memory', in Proceedings of the 33rd IEEE International Conference on Computer Design Iccd 2015, Institute of Electrical and Electronics Engineers (IEEE), New York, NY, USA, pp. 635 - 642, presented at IEEE International Conference on Computer Design (ICCD), New York, NY, USA, 18 October 2015 - 21 October 2015, http://dx.doi.org/10.1109/ICCD.2015.7357175
      Conference Papers | 2015
      Tang L; Ambrose JA; Kumar A; Parameswaran S, 2015, 'Dynamic reconfigurable puncturing for secure wireless communication', in Proceedings Design Automation and Test in Europe Date, pp. 888 - 891, http://dx.doi.org/10.7873/date.2015.0851
      Conference Papers | 2015
      Tang X; Kishore R; Parameswaran S, 2015, 'Dig deeper or diversify? The rewards and penalties of knowledge exploration and exploitation capabilities in the context of IS scholar publication productivity', in 2015 International Conference on Information Systems: Exploring the Information Frontier, ICIS 2015
      Conference Papers | 2015
      Zhang X; Haris J; Muhammad S; Jude Angelo A; Jörg H; Sri P, 2015, 'ADAPT: An ADAptive Manycore Methodology for Software Pipelined ApplicaTions', in ASP-DAC (ed.), presented at 20th Asia and South Pacific Design Automation Conference, 19 January 2015 - 22 January 2015
      Conference Papers | 2015
      Zhang X; Java H; Shafique M; Peddersen J; Henkel JO; Parameswaran S, 2015, 'E-pipeline: Elastic Hardware/Software Pipelines on a Many-Core Fabric', in DATE 15, Grenoble, France, presented at DATE 15, Grenoble, France, 09 March 2015 - 13 March 2015
      Conference Posters | 2015
      2015, 'Sequential C-code to Distributed Pipelined Heterogeneous MPSoC Synthesis for Streaming Applications'
      Conference Posters | 2015
      Shwe S; Batra K; Yachide Y; Peddersen JM; Parameswaran S, 2015, 'RAPITIMATE: Rapid Performance Estimation of Pipelined Processing Systems Containing Shared Memory'
      Conference Papers | 2014
      Aluthwala P; Weste N; Adams A; Lehmann T; Parameswaran S, 2014, 'A simple digital architecture for a harmonic-cancelling sine-wave synthesizer', in Proceedings IEEE International Symposium on Circuits and Systems, pp. 2113 - 2116, http://dx.doi.org/10.1109/ISCAS.2014.6865584
      Conference Papers | 2014
      Ambrose JA; Peddersen J; Parameswaran S; Labios A; Yachide Y, 2014, 'SDG2KPN: System Dependency Graph to function-level KPN generation of legacy code for MPSoCs', in Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC, pp. 267 - 273, http://dx.doi.org/10.1109/ASPDAC.2014.6742901
      Conference Papers | 2014
      Bokhari H; Javaid H; Shafique M; Henkel J; Parameswaran S, 2014, 'Darknoc: Designing energyefficient networkonchip with multivt cells for dark silicon', in Proceedings Design Automation Conference, http://dx.doi.org/10.1145/2593069.2593117
      Conference Papers | 2014
      Doan HC; Javaid H; Parameswaran S, 2014, 'Flexible and Scalable Implementation of H.264/AVC Encoder for Multiple Resolutions Using ASIPs', in Preas K (ed.), Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014, Institute of Electrical and Electronics Engineers ( IEEE ), Dresden, Germany, pp. 1791 - 1796, presented at DATE, Dresden, Germany, 24 March 2014 - 28 March 2014, http://www.proceedings.com/22046.html
      Conference Papers | 2014
      Doan HC; Javaid H; Parameswaran S, 2014, 'Flexible and scalable implementation of H.264/AVC encoder for multiple resolutions using ASIPs', in Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014, IEEE Conference Publications, pp. 1 - 6, presented at Design Automation and Test in Europe, 24 March 2014 - 28 March 2014, http://dx.doi.org/10.7873/date.2014.366
      Conference Papers | 2014
      Javaid H; Yachide Y; Shwe SMM; Bokhari H; Parameswaran S, 2014, 'FALCON: A Framework for HierarchicAL Computation of Metrics for CompONent-Based Parameterized SoCs', in Proceedings of the The 51st Annual Design Automation Conference on Design Automation Conference, ACM, pp. 33:1 - 33:6, http://dx.doi.org/10.1145/2593069.2593138
      Conference Papers | 2014
      Jayasinghe D; Ragel R; Ambrose JA; Ignjatovic A; Parameswaram S, 2014, 'Advanced Modes in AES: Are they Safe from Power Analysis based Side Channel Attacks?', Seoul, Korea, presented at IEEE International Conference on Computer Design, Seoul, Korea, 19 October 2014 - 22 October 2014
      Conference Papers | 2014
      Nawinne I; Schneider J; Javaid H; Parameswaran S, 2014, 'Hardware-based fast exploration of cache hierarchies in application specific MPSoCs', in Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014, IEEE Conference Publications, pp. 1 - 6, presented at Design Automation and Test in Europe, 24 March 2014 - 28 March 2014, http://dx.doi.org/10.7873/date.2014.296
      Conference Papers | 2014
      Nawinne I; Schneider J; Javaid H; Parameswaran S, 2014, 'Hardware-based fast exploration of cache hierarchies in application specific MPSoCs', in Proceedings Design Automation and Test in Europe Date, http://dx.doi.org/10.7873/DATE2014.296
      Conference Papers | 2014
      Parameswaran S, 2014, 'Mapping programs for execution on pipelined MPSoCs', in 2014 IEEE 12th Symposium on Embedded Systems for Real Time Multimedia Estimedia 2014, pp. 11, http://dx.doi.org/10.1109/ESTIMedia.2014.6962340
      Conference Papers | 2014
      Schneider JL; Peddersen J; Parameswaran S, 2014, 'A Scorchingly Fast FPGA-Based Precise L1 LRU Cache Simulator', in Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC 2014), IEEE, Singapore, pp. 412 - 417, presented at 2014 19th Asia and South Pacific Design Automation Conference, Singapore, 20 January 2014 - 23 January 2014, http://dx.doi.org/10.1109/ASPDAC.2014.6742926
      Conference Papers | 2014
      Schneider JL; Peddersen J; Parameswaran S, 2014, 'MASH{fifo}: A Hardware-Based Multiple Cache Simulator for Rapid FIFO Cache Analysis', in Proceedings of the The 51st Annual Design Automation Conference, ACM New York, NY, USA, San Francisco, California, USA, pp. 1 - 6, presented at The 51st Annual Design Automation Conference, San Francisco, California, USA, 01 June 2014 - 05 June 2014, http://dx.doi.org/10.1145/2593069.2593159
      Conference Papers | 2014
      Shafique M; Garg S; Mitra T; Parameswaran S; Henkel J, 2014, 'Dark silicon as a challenge for hardware/software co-design', in 2014 International Conference on Hardware Software Codesign and System Synthesis Codes Isss 2014, http://dx.doi.org/10.1145/2656075.2661645
      Preprints | 2014
      Shah SM; Parameswaran S; Sharma V, 2014, Previous Messages Provide the Key to Achieve Shannon Capacity in a Wiretap Channel, http://dx.doi.org/10.1109/ICCW.2013.6649323
      Conference Papers | 2014
      Tang L; Ambrose JA; Parameswaran S; Zhu S, 2014, 'Reconfigurable convolutional codec for physical layer communication security application', in Proceedings IEEE Military Communications Conference MILCOM, pp. 82 - 87, http://dx.doi.org/10.1109/MILCOM.2014.21
      Conference Papers | 2013
      Ambrose JA; Cassisi V; Murphy D; Li T; Jayasinghe D; Parameswaran S, 2013, 'Scalable performance monitoring of application specific multiprocessor Systems-on-Chip', in 2013 IEEE 8th International Conference on Industrial and Information Systems, ICIIS 2013 - Conference Proceedings, pp. 315 - 320, http://dx.doi.org/10.1109/ICIInfS.2013.6732002
      Conference Papers | 2013
      Amrouch H; Ebi T; Schneider JL; Parameswaran S; Henkel J, 2013, 'Analyzing the thermal hotspots in FPGA-based embedded systems', in 2013 23rd International Conference on Field Programmable Logic and Applications (FPL 2013), Porto, Portugal, presented at 23rd International Conference on Field Programmable Logic and Applications (FPL), 2013, Porto, Portugal, 02 September 2013 - 04 September 2013, http://dx.doi.org/10.1109/FPL.2013.6645567
      Conference Papers | 2013
      Bokhari H; Javaid H; Parameswaran S, 2013, 'System-level optimization of on-chip communication using express links for throughput constrained MPSoCs', in 2013 IEEE 11th Symposium on Embedded Systems for Real-time Multimedia (ESTIMedia 2013), Montreal, Canada, pp. 68 - 77, presented at ESTIMedia 2013 : The 11th IEEE Symposium on Embedded Systems for Real-time Multimedia, Montreal, Canada, 03 October 2013 - 04 October 2013
      Conference Papers | 2013
      Henkel J; Narayanan V; Parameswaran S; Teich J, 2013, 'Run-time adaption for highly-complex multi-core systems', in 2013 International Conference on Hardware Software Codesign and System Synthesis Codes Isss 2013, http://dx.doi.org/10.1109/CODES-ISSS.2013.6659000
      Conference Papers | 2013
      Min SM; Javaid H; Ignjatovic A; Parameswaran S, 2013, 'A case study on exploration of last-level cache for energy reduction in DDR3 DRAM', in Proceedings 2013 2nd Mediterranean Conference on Embedded Computing Meco 2013, pp. 42 - 45, http://dx.doi.org/10.1109/MECO.2013.6601372
      Conference Papers | 2013
      Muthukaruppan TS; Javaid H; Mitra T; Parameswaran S, 2013, 'Energy-aware synthesis of application specific MPSoCs', in 2013 IEEE 31st International Conference on Computer Design Iccd 2013, pp. 62 - 69, http://dx.doi.org/10.1109/ICCD.2013.6657026
      Conference Papers | 2013
      Nawinne I; Parameswaran S, 2013, 'A survey on exact cache design space exploration methodologies for application specific SoC memory hierarchies', in 8th IEEE International Conference on Industrial and Information Systems (ICIIS), 2013 - Conference Proceedings, IEEE, IEEE Xplore, pp. 332 - 337, presented at 8th IEEE International Conference on Industrial and Information Systems (ICIIS), 2013, Peradeniya, Sri Lanka, 17 December 2013 - 20 December 2013, http://dx.doi.org/10.1109/ICIInfS.2013.6732005
      Conference Papers | 2013
      Shah SM; Parameswaran S; Sharma V, 2013, 'Previous messages provide the key to achieve shannon capacity in a wiretap channel', in 2013 IEEE International Conference on Communications Workshops Icc 2013, pp. 697 - 701, http://dx.doi.org/10.1109/ICCW.2013.6649323
      Conference Papers | 2013
      Tang X; Parameswaran S; Kishore R; Herath TT, 2013, 'Simulation model of knowledge complexity in new knowledge transfer performance', in 19th Americas Conference on Information Systems Amcis 2013 Hyperconnected World Anything Anywhere Anytime, pp. 2980 - 2989
      Conference Papers | 2012
      Ambrose JA; Ignjatovic A; Parameswaran S, 2012, 'CoRaS: A Multiprocessor Key Corruption and Random Round Swapping for Power Analysis Side Channel Attacks: A DES Case Study', in ISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems Proceedings, IEEE, South Korea, pp. 253 - 256, presented at IEEE International Symposium on Circuits and Systems, South Korea, 20 May 2012, http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6271818
      Conference Papers | 2012
      Chan JS; Parameswaran S, 2012, 'NoCOUT : NoC topology generation with mixed packet-switched and point-to-point networks', in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, San Francisco, CA, presented at 2nd International Workshop on Computing in Heterogeneous, Autonomous 'N' Goal-oriented Environments. A workshop of the 49th Design Automation Conference (DAC 2012), San Francisco, CA, 03 June 2012 - 07 June 2012
      Conference Papers | 2012
      Haque ; Peddersen J; Janapsatya AG; Janapsatya A, 2012, 'SCUD: A Fast Singlepass L1 Cache Simulation Approach for Embedded Processors with Roundrobin Replacement Policy', in 2008 Asia and South Pacific Design Automation Conference, ASP-DAC, ACM, New York, NY, USA, pp. 356 - 361, presented at 2nd International Workshop on Computing in Heterogeneous, Autonomous 'N' Goal-oriented Environments. A workshop of the 49th Design Automation Conference (DAC 2012), San Francisco, CA, 03 June 2012 - 07 June 2012, http://dx.doi.org/10.1145/1837274.1837364
      Conference Papers | 2012
      Haque S; Ragel RG; Ambrose JA; Radhakrishnan S; Parameswaran S, 2012, 'DIMSim: A Rapid Two-level Cache Simulation Approach for Deadline-based MPSoCs', in The International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)), ACM, New York, USA, pp. 151 - 160, presented at The International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)), Tampere, Finland, 07 October 2012, http://dl.acm.org/citation.cfm?id=2380473
      Conference Papers | 2012
      Li T; Ambrose JA; Parameswaran S, 2012, 'Fine-grained Hardware/Software Methodology for Process Migration in MPSoCs', in Hu A (ed.), International Conference on Computer Aided Design (ICCAD), ACM, New York, USA, pp. 508 - 515, presented at IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, USA, 05 November 2012 - 08 November 2012, http://ieeexplore.ieee.org/xpl/articleDetails.jsp?reload=true&arnumber=6386717&contentType=Conference+Publications
      Conference Papers | 2012
      Parameswaran S; Valecha R; Sharman R; Rao HR; Singh R; Singh G, 2012, 'A prototype of a Patient Safety Knowledge Management System (PSKMS)', in 22nd Workshop on Information Technologies and Systems Wits 2012, pp. 241
      Conference Papers | 2011
      Chan JS; Parameswaran S, 2011, 'NOCEE: Energy macro-model extraction methodology for network on chip routers', in ICCAD 2010, San Jose, CA, United States, presented at 2011 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2011, San Jose, CA, United States, 07 November 2011 - 10 November 2011
      Conference Papers | 2011
      Doan H; Javaid H; Parameswaran S, 2011, 'Multi-ASIP based parallel and scalable implementation of motion estimation kernel for high definition videos', in 2011 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia, ESTIMedia 2011, IEEE, Piscataway, United States, pp. 56 - 65, presented at 2011 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia, ESTIMedia 2011, Taipei, Taiwan, 13 October 2011 - 14 October 2011, http://dx.doi.org/10.1109/ESTIMedia.2011.6088526
      Conference Papers | 2011
      Haque ; Peddersen JMD; Parameswaran S, 2011, 'CIPARSim: Cache Intersection Property Assisted Rapid Single-pass FIFO Cache Simulation Technique', in 2011 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2011, IEEE, New York, NY, United States, pp. 126 - 133, presented at 2011 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2011, San Jose, CA, United States, 07 November 2011 - 10 November 2011, http://dx.doi.org/10.1109/ICCAD.2011.6105316
      Conference Papers | 2011
      Javaid H; Shafique M; Parameswaran S; Henkel J, 2011, 'Low-power adaptive pipelined MPSoCs for multimedia: An H.264 video encoder case study', in Proceedings - Design Automation Conference, Institute of Electrical and Electronics Engineers Inc.,, San Diego, CA, United states, pp. 1032 - 1037, presented at 2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011, San Diego, CA, United states, 05 June 2011 - 09 June 2011
      Conference Papers | 2011
      Kamakoti V; Narayanan V; Sur-Kolay S; Parameswaran S, 2011, 'Welcome message from the symposium chairs', in Proceedings 2011 IEEE Computer Society Annual Symposium on VLSI Isvlsi 2011, http://dx.doi.org/10.1109/ISVLSI.2011.4
      Conference Papers | 2011
      Shwe SMM; Peddersen JMD; Parameswaran S, 2011, 'Realizing cycle accurate processor memory simulation via interface abstraction', in Proceedings of the IEEE International Conference on VLSI Design 2011, Chennai, India, pp. 141 - 146, presented at 24th International Conference on VLSI Design, VLSI Design 2011, Held Jointly with 10th International Conference on Embedded Systems, Chennai, India, 02 January 2011 - 07 January 2011, http://dx.doi.org/10.1109/VLSID.2011.36
      Conference Papers | 2010
      Avnit K; D Silva VV; Sowmya A; Ramesh S, 2010, 'A formal approach to the protocol converter problem', in Proceedings of the Design, Automation and Test in Europe Conference, European Design and Automation Association, 3001 Leuven, Belgium, Belgium, presented at Design, Automation and Test in Europe, Dresden, Germany, 08 March 2010 - 12 March 2010
      Conference Papers | 2010
      Haque ; Peddersen J; Janapsatya AG; Janapsatya A, 2010, 'DEW: A Fast Level 1 Cache Simulation Approach for Embedded Processors with FIFO Replacement Policy', in Proceedings of the Design, Automation and Test in Europe Conference, European Design and Automation Association, 3001 Leuven, Belgium, Belgium, pp. 496 - 501, presented at Design, Automation and Test in Europe, Dresden, Germany, 08 March 2010 - 12 March 2010, http://portal.acm.org/citation.cfm?id=1870926.1871044
      Conference Papers | 2010
      Haque MS; Janapsatya AG; Parameswaran S, 2010, 'SuSeSim: A FAST SIMULATION STRATEGY TO FIND OPTIMAL L1 CACHE CONFIGURATION FOR EMBEDDED SYSTEMS', in International Conference on Hardware/Software CoDesign and System Synthesis (CODES+ISSS 2010), Scottsdale, AZ, presented at 6th International Conference on Hardware/Software CoDesign and System Synthesis (CODES+ISSS 2010), Scottsdale, AZ, 24 October 2010 - 29 October 2010
      Conference Papers | 2010
      He X; Peddersen JM; Parameswaran S, 2010, 'LOP: A NOVEL SRAM-BASED ARCHITECTURE FOR LOW POWER AND HIGH THROUGHPUT PACKET CLASSIFICATION', in International Conference on Hardware/Software CoDesign and System Synthesis (CODES+ISSS 2010), Scottsdale, AZ, presented at 6th International Conference on Hardware/Software CoDesign and System Synthesis (CODES+ISSS 2010), Scottsdale, AZ, 24 October 2010 - 29 October 2010
      Conference Papers | 2010
      Janapsatya AG; Ignjatovic A; Peddersen J; Parameswaran S, 2010, 'Dueling CLOCK: Adaptive Cache Replacement Policy Based on the CLOCK Algorithm', in Proceedings of the Design, Automation and Test in Europe Conference, European Design and Automation Association, 3001 Leuven, Belgium, Belgium, presented at Design, Automation and Test in Europe, Dresden, Germany, 08 March 2010 - 12 March 2010, http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5456920&tag=1
      Conference Papers | 2010
      Javaid H; He X; Ignjatovic A; Parameswaran S, 2010, 'Optimal synthesis of latency and throughput constrained pipelined MPSoCs targeting streaming applications', in International Conference on Hardware/Software CoDesign and System Synthesis (CODES+ISSS 2010), Scottsdale, AZ, pp. 75 - 84, presented at 6th International Conference on Hardware/Software CoDesign and System Synthesis (CODES+ISSS 2010), Scottsdale, AZ, 24 October 2010 - 29 October 2010, http://dx.doi.org/10.1145/1878961.1878978
      Conference Papers | 2010
      Javaid H; Ignjatovic A; Parameswaran S, 2010, 'Fidelity metrics for estimation models', in ICCAD 2010, San Jose, CA, USA, pp. 1 - 8, presented at IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2010, San Jose, CA, USA, 07 November 2010 - 11 November 2010, http://dx.doi.org/10.1109/ICCAD.2010.5653959
      Conference Papers | 2010
      Javaid H; Janapsatya A; Haque ; Parameswaran S, 2010, 'Rapid Runtime Estimation Methods for Pipelined MPSoCs', in Design, Automation and Test in Europe, European Design and Automation Association, 3001 Leuven, Belgium, Belgium, pp. 363 - 368, presented at Design, Automation and Test in Europe, Dresden, Germany, 08 March 2010 - 12 March 2010, http://portal.acm.org/citation.cfm?id=1870926.1871015
      Conference Papers | 2010
      Ragel RG; Ambrose JA; Peddersen J; Parameswaran S, 2010, 'RACE: A Rapid, ArChitectural Simulation and Synthesis Framework for Embedded Processors', in IFIP AICT 329, Springer, Berlin, Germany, pp. 137 - 144, presented at 7th IFIP Conference on Distributed and Parallel Embedded Systems, Brisbane, Australia, 20 September 2010 - 23 September 2010, http://dx.doi.org/10.1007/978-3-642-15234-4_14
      Conference Papers | 2010
      Shee SL; Erdos A; Parameswaran S, 2010, 'Heterogenous Multiprocessor Implementations for JPEG: A Case Study', in International Conference on Hardware/Software CoDesign and System Synthesis (CODES+ISSS 2010), Scottsdale, AZ, presented at 6th International Conference on Hardware/Software CoDesign and System Synthesis (CODES+ISSS 2010), Scottsdale, AZ, 24 October 2010 - 29 October 2010
      Conference Papers | 2009
      Chong Y; Parameswaran S, 2009, 'Flexible Multi-Mode embedded Floating Point Unit for Field Programmable Gate Arrays', in Proceedings of the 7th ACM SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA`09, Monterey, CA, USA, presented at International Symposium on Field Programmable Gate Arrays (FPGA `09), Monterey, CA, USA, 22 February 2009 - 24 February 2009
      Conference Papers | 2009
      He X; Peddersen JM; Parameswaran S, 2009, 'LOP_RE: RANGE ENCODING FOR LOW POWER PACKET CLASSIFICATION', in PROCEEDINGS OF IEEELCN 2009, IEEE, Zurich, Switzerland, presented at 34th IEEE Conference on Local Computer networks(IEEE LCN) 2009, Zurich, Switzerland, 20 October 2009 - 23 October 2009
      Conference Papers | 2009
      Henkel J; Narayanan V; Parameswaran S; Ragel R, 2009, 'Security and Dependability of Embedded Systems: A Computer Architects' Perspective', in 22ND INTERNATIONAL CONFERENCE ON VLSI DESIGN HELD JOINTLY WITH 8TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, PROCEEDINGS, IEEE COMPUTER SOC, INDIA, New Delhi, pp. 30 - 32, presented at 22nd International Conference on VLSI Design held with 8th International Conference on Embedded Systems, INDIA, New Delhi, 05 January 2009 - 09 January 2009, http://dx.doi.org/10.1109/VLSI.Design.2009.114
      Conference Papers | 2009
      Henkel J; Parameswaran S, 2009, 'Message from the CASES 2009 Conference Chairs', in Embedded Systems Week 2009 2009 International Conference on Compilers Architecture and Synthesis for Embedded Systems Cases 09
      Conference Papers | 2009
      Janapsatya AG; Ignjatovic A; Parameswaran S, 2009, 'HitME: Low power hit memory buffer for embedded systems', tokyo, tokyo, http://portal.acm.org/citation.cfm?id=1509633.1509720&coll=GUIDE&dl=ACM&type=series&idx=SERIES480&part=series&WantType=Proceedings&title=ASPDAC
      Conference Papers | 2009
      Javaid H; Parameswaran S, 2009, 'A DESIGN FLOW FOR APPLICATION SPECIFIC HETEROGENEOUS PIPELINED MULTIPROCESSOR SYSTEMS', in Proceedings of the 46th Design Automation Conference, The Association for Computing Machinery, New York, NY, USA, presented at Design Automation Conference, SAN FRANCISCO, USA, http://dx.doi.org/10.1145/1629911.1629979
      Conference Papers | 2009
      Patel K; Parameswaran S; Ragel R, 2009, 'CUFFS: An Instruction Count Based Architectural framework for Security of MPSOC`s', in proceedings of the Design Automation and Test in Europe, KP Publications, Nice, France, presented at Design, Automation & Test in Europe Conference & Exhibition, 2009, Date `09, Nice, France, 20 April 2009 - 24 April 2009
      Conference Papers | 2008
      Altman E; Parameswaran S, 2008, 'Embedded Systems Week 2008 - Proceedings of the 2008 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES'08: Foreword', in Embedded Systems Week 2008 - Proceedings of the 2008 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES'08
      Conference Papers | 2008
      Ambrose JA; Parameswaran S; Ignjatovic A, 2008, 'MUTE-AES: a multiprocessor architecture to prevent power analysis based side channel attacks of the AES algorithm', in International conference on computer aided design, San Jose, California USA, presented at International conference on computer aided design, San Jose, California USA, 10 November 2008 - 13 November 2008
      Conference Papers | 2008
      Avnit K; D'Silva V; Sowmya A; Ramesh S; Parameswaran S, 2008, 'A formal approach to the protocol converter problem', in Proceedings of the conference on Design, automation and test in Europe, ACM, pp. 294 - 299, presented at DATE '08: Design, Automation and Test in Europe, http://dx.doi.org/10.1145/1403375.1403447
      Conference Papers | 2008
      Chong Y; Parameswaran S, 2008, 'Rapid application specific floating-point unit generation with bit-alignment', in 45th design automation conference, Anaheim, California, presented at 45th design automation conference, Anaheim, California, 08 June 2008 - 13 June 2008
      Conference Papers | 2008
      Chong YJ; Parameswaran S, 2008, 'Rapid application specific floating-point unit generation with bit-alignment', in Proceedings of the 45th annual Design Automation Conference, ACM, pp. 62 - 67, presented at DAC '08: The 45th Annual Design Automation Conference 2008, http://dx.doi.org/10.1145/1391469.1391487
      Conference Papers | 2008
      He X; Parameswaran S, 2008, 'MCAD: Multiple connection based anomaly detection', in The Eleventh IEEE International Conference on Communication Systems Proceedings, Guangzhou, China, presented at 11th IEEE International Conference on Communication Systems, Guangzhou, China, 19 November 2008 - 21 November 2008
      Conference Papers | 2008
      Parameswaran S; Javaid H, 2008, 'Synthesis of heterogeneous pipelined multiprocessor systems using ILP: JPEG case study', in CODES + ISS20 08, Atlanta, Georgia USA, presented at CODES + ISSS 2008, Atlanta, Georgia USA, 19 October 2008 - 24 October 2008
      Conference Papers | 2008
      Patel K; Parameswaran S, 2008, 'LOCS: a low overhead profiler-driven design flow for security of MPSoCs', in CODES + ISS20 08, Atlanta, Georgia USA, presented at CODES + ISSS 2008, Atlanta, Georgia USA, 19 October 2008 - 24 October 2008
      Conference Papers | 2008
      Patel K; Parameswaran S, 2008, 'SHIELD', in Proceedings of the 45th annual Design Automation Conference, ACM, pp. 858 - 861, presented at DAC '08: The 45th Annual Design Automation Conference 2008, http://dx.doi.org/10.1145/1391469.1391686
      Conference Papers | 2008
      Patel K; Parameswaran S, 2008, 'SHIELD: a software hardware design methodology for security and reliability of MPSoCs', in 45th design automation conference, Anaheim, California, presented at 45th design automation conference, Anaheim, California, 08 June 2008 - 13 June 2008
      Conference Papers | 2007
      Ambrose JA; Ragel RG; Parameswaran S, 2007, 'RIJID', in Proceedings of the 44th annual conference on Design automation - DAC '07, ACM Press, pp. 489 - 489, presented at the 44th annual conference, 04 June 2007 - 08 June 2007, http://dx.doi.org/10.1145/1278480.1278606
      Conference Papers | 2007
      Ambrose JA; Ragel RG; Parameswaran S, 2007, 'RIJID: random code injection to mask power analysis based side channel attacks', in 44th Design automation conference, San Diego, Californa, USA, presented at 44th Design automation conference, San Diego, Californa, USA, 04 June 2007 - 08 June 2007
      Conference Papers | 2007
      Chong Y; Parameswaran S, 2007, 'Automatic application specific floating-point unit generation', in Design, automation and test in Europe 2007, Munich, Germany, presented at Design, automation and test in Europe 2007, Munich, Germany, 16 April 2007 - 20 April 2007
      Conference Papers | 2007
      Janapsatya AG; Ignjatovic A; Parameswaran S; Henkel J, 2007, 'Instruction trace compression for rapid instruction cache simulation', in Design, automation and test in Europe 2007, Munich, Germany, presented at Design, automation and test in Europe 2007, Munich, Germany, 16 April 2007 - 20 April 2007, http://dx.doi.org/10.1109/DATE.2007.364389
      Conference Papers | 2007
      Parameswaran S; Ragel RG; Ambrose JA, 2007, 'A smart random code injection to mask power analysis based side channel attacks', in CODES + ISSS 2007: International conference on hardware/software codesign and systems synthesis, Salsburg, Austria, presented at CODES + ISSS 2007: International conference on hardware/software codesign and systems synthesis, Salsburg, Austria, 30 September 2007 - 03 October 2007
      Conference Papers | 2007
      Patel K; Parameswaran S; Shee SL, 2007, 'Ensuring secure program execution in multiprocessor embedded systems: a case study', in CODES + ISSS 2007: International conference on hardware/software codesign and systems synthesis, Salsburg, Austria, presented at CODES + ISSS 2007: International conference on hardware/software codesign and systems synthesis, Salsburg, Austria, 30 September 2007 - 03 October 2007
      Conference Papers | 2007
      Peddersen JM; Parameswaran S, 2007, 'Clipper: counter-based low impact processor power estimation at run-time', in 12th Asia and South-Pacific design automation conference, Yokohama, Japan, presented at 12 Asia and South-Pacific design automation conference, Yokohama, Japan, 23 January 2007 - 26 January 2007
      Conference Papers | 2007
      Peddersen JM; Parameswaran S, 2007, 'Energy driven application self-adaptation at run-time', in 20th international conference on VLSI design, Bangalore, India, presented at 20th international conference on VLSI design, Bangalore, India, 06 January 2007 - 10 January 2007
      Conference Papers | 2007
      Shee SL; Parameswaran S, 2007, 'Design methodology for pipelined heterogeneous multiprocessor system', in 44th Design automation conference, San Diego, Californa, USA, presented at 44th Design automation conference, San Diego, Californa, USA, 04 June 2007 - 08 June 2007
      Conference Papers | 2007
      Shee SL; Parameswaran S, 2007, 'Design methodology for pipelined heterogeneous multiprocessor system', in Proceedings of the 44th annual conference on Design automation - DAC '07, ACM Press, pp. 811 - 811, presented at the 44th annual conference, 04 June 2007 - 08 June 2007, http://dx.doi.org/10.1145/1278480.1278682
      Conference Papers | 2006
      Janapsatya A; Ignjatović A; Parameswaran S, 2006, 'A novel instruction scratchpad memory optimization method based on concomitance metric', in Proceedings of the 2006 conference on Asia South Pacific design automation - ASP-DAC '06, ACM Press, pp. 612 - 612, presented at the 2006 conference, 24 January 2006 - 27 January 2006, http://dx.doi.org/10.1145/1118299.1118443
      Conference Papers | 2006
      Janapsatya A; Ignjatović A; Parameswaran S, 2006, 'Finding optimal L1 cache configuration for embedded systems', in Proceedings of the 2006 conference on Asia South Pacific design automation - ASP-DAC '06, ACM Press, pp. 796 - 796, presented at the 2006 conference, 24 January 2006 - 27 January 2006, http://dx.doi.org/10.1145/1118299.1118482
      Conference Papers | 2006
      Janapsatya AG; Ignjatovic A; Parameswaran S, 2006, 'A novel instruction scratchpad memory optimization method based on concomitance metric', in ASPDAC 2006, Yokohama, Japan, presented at ASPDAC 2006, Yokohama, Japan, 24 January 2006 - 27 January 2006
      Conference Papers | 2006
      Janapsatya AG; Ignjatovic A; Parameswaran S, 2006, 'Finding optimal L1 cache configuration for embedded systems', in ASPDAC 2006, Yokohama, Japan, presented at ASPDAC 2006, Yokohama, Japan, 24 January 2006 - 27 January 2006
      Conference Papers | 2006
      Lu IS; Weste N; Parameswaran S, 2006, 'ADC precision requirement for digital ultra-wideband receivers with sublinear front-ends: A power and performance perspective', in Proceedings of the VLSI Design Conferences, India, presented at 19th Conference on VLSI Design, India, 03 January 2006 - 07 January 2006, http://dx.doi.org/10.1109/VLSID.2006.32
      Conference Papers | 2006
      Parameswaran S; Ragel RG, 2006, 'IMPRES: integrated monitoring for processor reliability and security', in 43rd Design automation conference 2006, San Francisco, California USA, presented at 43rd Design automation conference 2006, San Francisco, California USA, 24 July 2006 - 28 July 2006
      Conference Papers | 2006
      Radhakrishnan S; Guo H; Parameswaran S; Ignjatovic A, 2006, 'Application specific forwarding network and instruction encoding for multi-pipe ASIPs', in Codes Isss 2006 Proceedings of the 4th International Conference on Hardware Software Codesign and System Synthesis, pp. 241 - 246, http://dx.doi.org/10.1145/1176254.1176313
      Conference Papers | 2006
      Radhakrishnan S; Guo HA; Parameswaran S, 2006, 'Customization of application specific heterogeneous multi-pipeline processors', in 43rd Design automation conference, Munich, Germany, presented at 43rd Design automation conference, Munich, Germany, 06 March 2006 - 10 March 2006
      Conference Papers | 2006
      Radhakrishnan S; Hui Guo ; Parameswaran S, 2006, 'Customization of application specific heterogeneous multi-pipeline processors', in Proceedings of the Design Automation & Test in Europe Conference, IEEE, pp. 6 pp. - 6 pp., presented at 2006 Design, Automation and Test in Europe, 06 March 2006 - 10 March 2006, http://dx.doi.org/10.1109/date.2006.244094
      Conference Papers | 2006
      Ragel RG; Parameswaran S, 2006, 'Hardware assisted pre-emptive control flow checking for embedded processors to improve reliability', in Codes Isss 2006 Proceedings of the 4th International Conference on Hardware Software Codesign and System Synthesis, pp. 100 - 105, http://dx.doi.org/10.1145/1176254.1176280
      Conference Papers | 2006
      Wu H; Parameswaran S, 2006, 'Minimising the energy consumption of real-time tasks with precedence constraints on a single processor', in Embedded and ubiquitous computing 2006, Seoul, South Korea, presented at Embedded and ubiquitous computing 2006, Seoul, South Korea, 01 August 2006 - 04 August 2006
      Conference Papers | 2005
      Cheung N; Parameswaran S; Henkel J, 2005, 'Battery aware instruction generation for embedded processors', in ASP-DAC 2005: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, IEEE, PEOPLES R CHINA, Shanghai, pp. 553 - 556, presented at 10th Asia and South Pacific Design Automation Conference, PEOPLES R CHINA, Shanghai, 18 January 2005 - 21 January 2005, http://dx.doi.org/10.1145/1120725.1120960
      Conference Papers | 2005
      Guo HA; Parameswaran S, 2005, 'Balancing system level pipelines with stage voltage scaling', in IEEE annual symposium on VLSI, Tampa, Florida, USA, presented at IEEE annual symposium on VLSI, Tampa, Florida, USA, 11 May 2005 - 12 May 2005
      Conference Papers | 2005
      Lu IS; Weste N; Parameswaran S, 2005, 'The effect of receiver front-end non-linearity on DS-UWB systems operating in the 3 to 4GHz band', in IEEE Wireless communications and networking conference, New Orleans, Louisiana, USA, presented at IEEE Wireless Communications and Networking Conference WCNC 2005, New Orleans, Louisiana, USA, 13 March 2005 - 17 March 2005
      Conference Papers | 2005
      Peddersen JM; Shee SL; Janapsatya AG; Parameswaran S, 2005, 'Rapid embedded hardware/software system generation', in 18th international conference on VLSI design 2005, Kolkata, India, presented at 18th international conference on VLSI design 2005, Kolkata, India, 03 January 2005 - 07 January 2005
      Conference Papers | 2005
      Ragel RG; Parameswaran S; Kia S, 2005, 'Micro monitoring for security in application specific instruction-set processors', in International conference on compilers, architectures and synthesis for embedded systems, San Francisco, California USA, presented at International Conference on Compilers, Architecture, and Synthesis for Embedded Systems 2006, San Francisco, California USA, 24 September 2005 - 27 September 2005
      Conference Papers | 2005
      Shee SL; Parameswaran S; Cheung NL, 2005, 'Novel architecture for loop acceleration: A case study', in international conference on hardware/software codesign, Jersey City, NJ, USA, presented at International Conference on Hardware/Software Code Design 2005, Jersey City, NJ, USA, 19 September 2005 - 21 September 2005
      Conference Papers | 2004
      Chan JS; Parameswaran S, 2004, 'NoCGEN: a template based reuse methodology for networks on chip architecture', in 17th International Conference on VLSI Design, Mumbai India, presented at 17th International Conference on VLSI Design, Mumbai India, 05 January 2004 - 09 January 2004
      Conference Papers | 2004
      Cheung NL; Parameswaran S; Henkel J; Chan JS, 2004, 'MINCE: Matching INstructions with Combinational Equivalence for Extensible Processor', in Proceedings Design, Automation and Test in Europe Conference and Exhibition, IEEE, Paris, France, presented at Design Automation and Test in Europe (DATE), Paris, France, 16 February 2004 - 20 February 2004
      Conference Papers | 2004
      Cheung NL; Parameswaran S; Henkel J, 2004, 'A Quantitative Study and Estimation Models for Extensible Instructions in Embedded Processors', in ICCAD2004 (International Conference on Computer Aided Design), San Jose, California USA, presented at ICCAD2004 (International Conference on Computer Aided Design), San Jose, California USA, 07 November 2004 - 11 November 2004
      Conference Papers | 2004
      Janapsatya AG; Parameswaran S; Ignjatovic A, 2004, 'Hardware/Software managed scratchpad memory for embedded systems', in ICCAD2004 (International Conference on Computer Aided Design), San Jose, California USA, presented at ICCAD2004 (International Conference on Computer Aided Design), San Jose, California USA, 07 November 2004 - 11 November 2004
      Conference Papers | 2004
      Parameswaran S; Guo HA; Radhakrishnan S, 2004, 'Dual-Pipeline Heterogeneous ASIP Design', in CODES + ISSS 2004, Stockholm, Sweden, presented at CODES + ISSS 2004, Stockholm, Sweden, 08 September 2004 - 10 September 2004
      Conference Papers | 2003
      Chandra R; Henkel J; Panda PR; Parameswaran S; Ramachandran L, 2003, 'Specification and design of multi-million gate SOCs', in 16TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, IEEE COMPUTER SOC, INDIA, NEW DELHI, pp. 18 - 19, presented at 16th International Conference on VLSI Design/2nd International Conference on Embedded Systems Design, INDIA, NEW DELHI, 04 January 2003 - 08 January 2003, http://dx.doi.org/10.1109/ICVD.2003.1183107
      Conference Papers | 2003
      Cheung N; Henkel J; Parameswaran S, 2003, 'Rapid Configuration & Instruction Selection for an ASIP: A Case Study', Institute of Electrical and Electronics Engineers (IEEE), pp. 1 - 6, presented at 2003 Design, Automation and Test in Europe Conference and Exhibition, http://dx.doi.org/10.1109/date.2003.1253705
      Conference Papers | 2003
      Cheung N; Henkel J; Parameswaran S, 2003, 'Rapid configuration & instruction selection for an ASIP: A case study', in DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, PROCEEDINGS, IEEE COMPUTER SOC, GERMANY, MUNICH, pp. 802 - 807, presented at Design, Automation and Test in Europe Conference and Exhibition (DATE 03), GERMANY, MUNICH, 03 March 2003 - 07 March 2003
      Conference Papers | 2003
      Cheung NL; Parameswaran S; Henkel J, 2003, 'INSIDE: Instruction Selection/Identification & Design Exploration for Extensible Processors', in 18th IEEE International Conference on Data Engineering (ICDE 2002), San Jose, California USA, presented at 18th IEEE International Conference on Data Engineering (ICDE 2002), San Jose, California USA, 09 November 2003 - 13 November 2003
      Conference Papers | 2003
      Lu IS; Weste N; Parameswaran S, 2003, 'A Digital Ultra-Wideband Multiband Transceiver Architecture with Fast Frequency Hopping Capabilities', in 2003 IEEE Conference on Ultra Wideband Systems and Technologies, Reston, Virginia, USA, presented at IEEE Conference on Ultra Wideband Systems and Technologies 2003, Reston, Virginia, USA, 16 November 2003 - 19 November 2003
      Conference Papers | 2003
      Parameswaran S; Henkel J; Lekastas H, 2003, 'Multi-parametric improvements for embedded systems using code-placement and address bus coding', in Proceedings of the 2003 conference on Asia South Pacific design automation - ASPDAC, ACM Press, pp. 15 - 15, presented at the 2003 conference, 21 January 2003 - 24 January 2003, http://dx.doi.org/10.1145/1119772.1119776
      Conference Papers | 2003
      Parameswaran S; Henkel J; Lekastas H, 2003, 'Multi-parametric improvements for embedded systems using code-placement and address bus coding', in Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC, pp. 15 - 21, http://dx.doi.org/10.1109/ASPDAC.2003.1194987
      Conference Papers | 2002
      , 2002, 'Proceedings of the tenth international symposium on Hardware/software codesign - CODES '02', ACM Press, presented at the tenth international symposium, 06 May 2002 - 08 May 2002, http://dx.doi.org/10.1145/774789
      Conference Papers | 2002
      Parameswaran S, 2002, 'SWASAD: an ASIC design for high speed DNA sequence matching', in ASP-DAC/VLSI-Design-2002.-7th-Asia-and-South-Pacific-Design-Automation-Conference-and-15h-International-Conference-on-VLSI-Design. 2002, Bangalore, India, presented at ASP-DAC/VLSI-Design-2002.-7th-Asia-and-South-Pacific-Design-Automation-Conference-and-15h-International-Conference-on-VLSI-Design. 2002, Bangalore, India, 07 January 2002 - 11 January 2002
      Conference Papers | 2001
      Parameswaran S, 2001, 'Code placement in hardware software Co synthesis to improve performance and reduce cost', in Proceedings Design Automation and Test in Europe Date, pp. 626 - 632, http://dx.doi.org/10.1109/DATE.2001.915089
      Conference Papers | 2000
      Boros VE; Rakic AD; Parameswaran S, 2000, 'High-level model of a WDMA passive optical bus for a reconfigurable multiprocessor system', in Proceedings Design Automation Conference, pp. 221 - 226, http://dx.doi.org/10.1145/337292.337395
      Conference Papers | 2000
      Rae A; Parameswaran S, 2000, 'Voltage reduction of application-specific heterogeneous multiprocessor systems for power minimisation', in Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC, pp. 147 - 152, http://dx.doi.org/10.1145/368434.368594
      Conference Papers | 1998
      Rae A; Parameswaran S, 1998, 'Application-specific heterogeneous multiprocessor synthesis using differential-evolution', in Proceedings of the International Symposium on System Synthesis, pp. 83 - 88, http://dx.doi.org/10.1109/isss.1998.730602
      Conference Papers | 1997
      Guo H; Parameswaran S, 1997, 'Unfolding loops with interdetermine count in system level pipelines', in Proceedings of the Australian Microelectronics Conference, pp. 82 - 87
      Conference Papers | 1997
      Parameswaran S; Guo H, 1997, 'Partitioning of system level pipelines', in Proceedings of the Australian Microelectronics Conference, pp. 233 - 238
      Conference Papers | 1997
      Parameswaran S; Guo H, 1997, 'Power consumption in CMOS combinational logic blocks at high frequencies', in Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC, pp. 195 - 200
      Conference Papers | 1997
      Parameswaran S; Guo H, 1997, 'Power reduction in pipelines', in Proceedings of the Australian Microelectronics Conference, pp. 239 - 244
      Conference Papers | 1995
      Jha P; Parameswaran S; Dutt N, 1995, 'Reclocking for high level synthesis', in Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC, pp. 49 - 54
      Conference Papers | 1995
      Parkinson MF; Parameswaran S, 1995, 'Profiling in the ASP codesign environment', in Proceedings of the International Symposium on System Synthesis, pp. 128 - 133, http://dx.doi.org/10.1145/224486.224531
      Conference Papers | 1994
      Kia SM; Parameswaran S, 1994, 'Design automation of self checking circuits', in European Design Automation Conference Proceedings, pp. 252 - 257
      Conference Papers | 1994
      Kia SM; Parameswaran S, 1994, 'Novel architectures for TSC/CD and SFS/SCD synchronous controllers', in Proceedings of the IEEE VLSI Test Symposium, pp. 138 - 143
      Conference Papers | 1994
      Parkinson MF; Taylor PM; Parameswaran S, 1994, 'C to VHDL converter in a codesign environment', in Spring 1994 Conference Proceedings VHDL International Users Forum VIUF 1994, pp. 100 - 109, http://dx.doi.org/10.1109/VIUF.1994.323960
      Theses / Dissertations | 1991
      Parameswaran S, 1991, SPOT : A computer aided digital design system, http://dx.doi.org/10.14264/uql.2015.616
      Conference Papers |
      Cheung N; Parameswarant S; Henkel J, 'Battery aware instruction generation for embedded processors', in Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005., IEEE, pp. 553 - 556, presented at ASP-DAC 2005. Asia and South Pacific Design Automation Conference 2005, http://dx.doi.org/10.1109/aspdac.2005.1466225
      Conference Papers |
      Parkinson MF; Parameswaran S, 'Profiling in the ASP codesign environment', in Proceedings of the Eighth International Symposium on System Synthesis, IEEE Comput. Soc. Press, pp. 128 - 133, presented at Eighth International Symposium on System Synthesis, http://dx.doi.org/10.1109/isss.1995.520624
      Conference Papers |
      Rae A; Parameswaran S, 'Voltage reduction of application-specific heterogeneous multiprocessor systems for power minimisation', in Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106), IEEE, pp. 147 - 152, presented at ASP-DAC2000: Asia and South Pacific Design Automation Conference 2000, http://dx.doi.org/10.1109/aspdac.2000.835086

    Title: ARC Research Hub for Connected Sensors for Health

    Source: ARC Industrial Transformation Research Hubs

    Amount: $5,000,000 from ARC and approximately $5,000,000 from Industry

    Year:2021-2026

    Involvement: as Chief Investigator (with others from four universities)

     

    Title: ARC Industry Transformation Research Hub for Resilient and Intelligent Infrastructure Systems (RIIS) in Urban, Resources and Energy Sectors.Source: ARC Industrial Transformation Research Hubs

    Amount: $4,980,000 from ARC and approximately $5,000,000 from Industry

    Year:2021-2026

    Involvement: as Chief Investigator (with others from four universities)

     

    Title: Design automation for secure, reliable and energy efficient embedded processors.

    Source: ARC DP

    Amount: $490,000

    Year:2019-2021

    Involvement: as sole principal investigator

     

    Title: Approximate algorithms and architectures for area efficient system design

    Source: ARC LP

    Amount: $468,522

    Year: 2018-2020

    Involvement: as the first named CI with Alex Ignjatovic

     

    Title: Towards a block-cipher circuit resistant to multiple side channel attacks

    Source: ARC DP

    Amount: $382,816

    Year:2018-2020

    Involvement: as the first named CI with Alex Ignjatovic

     

    Title: Trustworthy Computation Platform

    Source: DSTG

    Amount: $325,659

    Year: 2018-2019

    Involvement: as sole principal investigator

     

    Title: AIF Research Project

    Source: Canon

    Amount: $300,000

    Year: 2017

    Involvement: as sole principal investigator

     

    Title: Trustworthy Systems

    Source: DSTG

    Amount: $238,000

    Year: 2016/2017

    Involvement: as sole principal investigator

     

    Title: AIF Research Project

    Source: Canon

    Amount: $444,000

    Year: 2016

    Involvement: as sole principal investigator

     

    Title: DNA Sequencing on a Benchtop

    Source: Silver star

    Amount: $30,000

    Year: 2016

    Involvement: as the first named CI with Bruno Gaeta, Aleksandar Ignjatovic

     

    Title: AIF Research Project

    Source: Canon

    Amount: $446,000

    Year: 2015

    Involvement: as sole principal investigator

     

    Title: Greening of Dark Silicon – A Network-on-Chip Perspective

    Source: Gold star Sri Parameswaran

    Amount: $40,000

    Year: 2015

    Involvement: as sole principal investigator

     

    Title: AIF – Phase 3

    Source: Canon Information Systems Research Australia Pty Ltd

    Amount: $442,000

    Year: 2015

    Involvement: as sole principal investigator

     

    Title: Designing Radiation Tolerant Reconfigurable Systems for Space

    Source: Australian Research Council —Discovery

    Amount: $340,000

    Year: 2015-2017

    Involvement: as the first-named CI with Prof Andrew Dempster, Dr Oliver Diessel, Dr Angelo Ambrose and Dr Ediz Cetin

     

    Title: AIF – Phase 2

    Source: Canon Information Systems Research Australia Pty Ltd

    Amount: $618,000

    Year: 2014

    Involvement: as sole principal investigator

     

    Title: HPPSA – Phase3 / AIF Phase 1 Extension

    Source: Canon Information Systems Research Australia Pty Ltd

    Amount: $239,000

    Year: 2013

    Involvement: as sole principal investigator

     

    Title: HPPSA – Phase3 / AIF Phase 1

    Source: Canon Information Systems Research Australia Pty Ltd

    Amount: $720,000

    Year: 2012

    Involvement: as sole principal investigator

     

    Title: Low Power Memory for Modern Embedded Systems

    Source: Australian Research Council —Discovery

    Amount: $280,000

    Year: 2012-2014

    Involvement: as sole principal investigator

     

    Title: A Predictable and Reliable Runtime Task Migration for Variability aware Real time Multiprocessor System on Chip Embedded Systems.

    Source UNSW Goldstar

    Amount: $40,000

    Year: 2012

    Involvement: as CI with Dr Jude Angelo Ambrose

     

    Title: HPPSA - Phase 2

    Source: Canon Information Systems Research Australia Pty Ltd

    Amount: $370,000

    Year: 2012

    Involvement: as sole principal investigator

     

    Title: HPPSA - Phase 1

    Source: Canon Information Systems Research Australia Pty Ltd

    Amount: $355,000

    Year: 2011

    Involvement: as sole principal investigator

     

    Title: Long term Synopsys Design Suite Licence

    Source: University of New South Wales/Major Equipment & Infrastructure Scheme (MREII)

    Amount: :$76,000

    Year: 2012

    As Investigator with Dr Oliver Diessel, Dr Jorgen Peddersen, and Dr Annie Guo  

     

    Title: Bahurupi: Polymorphic Heterogeneous Multi-Core Systems:

    Source: Ministry of Education of Singapore

    Amount: :S$806,020

    Year: 2010 – 2012

    As Investigator with A/Prof Tulika Mitra (of National Uni. Of Singapore)

     

    Title: Design Automation for Processor Pipelines

    Source: Australian Research Council —Discovery

    Amount: $305,000

    Year: 2009-2011

    Involvement: as sole principal investigator

     

    Title: Design of Highly Secure Embedded Processors

    Source: UNSW Goldstar

    Amount $40,000

    Year: 2008

    Involvement: as CI with Dr A Ignjatovic and Dr A Janapsatya

     

    Title: Novel Multi-Processor Architectures for Steaming Applications in Embedded Systems

    Source: UNSW Goldstar

    Amount $40,000

    Year: 2008

    Involvement: as sole Chief Investigator

     

    Title: Sun Fire T2000 computer platform, which features an eight Core, 1.4 GHz UltraSPARC T1 processor

    Amount: 107,000

    Year: 2008

    Involvement: As Investigator with J.Xue et.al

     

    Title: Automatic Co-Processor Synthesis for ASIPs

    Source: Australian Research Council —Discovery

    Amount: $263,000

    Year: 2005-2007

    Involvement: as sole Chief Investigator

     

    Title: Provably Correct on-chip Communication-based Design

    Source: Australian Research Council —Discovery

    Amount: $203,000

    Year: 2005-2007

    Involvement: as CI with A/Prof A Sowmya, A/Prof A Nymeyer,  and Prof S Ramesh

     

    Title: ISIS Project

    Source: Canon Information Systems Research Australia Pty Ltd

    Amount: $246,000

    Year: 2005

    Involvement: as sole investigator

     

    Title: IPv6 Chip Design Project – Phase IV

    Source: Canon Information Systems Research Australia Pty Ltd

    Amount: $294,000

    Year: 2004

    Involvement: as sole investigator

     

    Title: IPv6 Chip Design Project – Phase III

    Source: Canon Information Systems Research Australia Pty Ltd

    Amount: $335,000

    Year: 2003

    Involvement: as sole investigator

     

    Title: Embedded Systems and Circuit Design Infrastructure

    Source: University of New South Wales Infrastructure Grants

    Amount: $80,000

    Year: 2003

    Involvement: as principal investigator

     

    Title: IPv6 Chip Design Project - Phase II

    Source: Canon Information Systems Research Australia Pty Ltd

    Amount: $107,000

    Year: July 2002 to Dec 2002

    Involvement: as principal investigator with Mahbub Hassan and Sanjay Jha

     

    Title: IPv6 Chip Design Project - Phase I

    Source: Canon Information Systems Research Australia Pty Ltd

    Amount: $143,000

    Year: Oct 2001 to June 2002

    Involvement: as principal investigator with Mahbub Hassan and Sanjay Jha

     

    Title: The Australian Research Council Special Research Centre for Functional and Applied Genomics

    Source: Australian Research Council

    Amount: $3,200,000

    Year: 1999-2001

    Involvement: as senior research associate

     

     

    Best Paper Award - Metamako Award 2019 for the best paper in the School of Computer Science and Engineering, UNSW

    Best Paper Award – CASES 2018

    Dean’s runner-up award for best paper in faculty – 2012 

    Best Paper Award – VLSI Design 2013

    CiSRA Best Paper Award – 2007

    Best Paper Nomination at ICCAD (William McCalla Award)

    Best Paper Nominations at VLSI Design

    Best Paper Nominations at ASP-DAC

    HiPEAC Awards 2014 (awarded in 2015), 2011

    Supervisor of the Year by the UNSW Postdoctoral Academy in 2013

    Awarded the UNSW Faculty of Engineering Teaching Staff Excellence Award in 2005

    Department of Electrical Engineering Postgraduate Research Scholarship
    The University of Queensland Postgraduate Research Scholarship

    Professor Sri Parameswaran is from the School of Computer Science and Engineering.

    Research interests include:

    • Hardware Software Co-Design
    • VLSI Systems
    • Low Power Design
    • Embedded Architectures for Bioinformatics
    • Hardware Security
    • Approximate Computing